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    X-RAY IMAGING APPARATUS AND METHOD OF CONTROLLING THE SAME
    1.
    发明申请
    X-RAY IMAGING APPARATUS AND METHOD OF CONTROLLING THE SAME 有权
    X射线成像装置及其控制方法

    公开(公告)号：US20140185766A1

    公开(公告)日：2014-07-03

    申请号：US14144766

    申请日：2013-12-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Hoon KANG ,  Dong Goo KANG ,  Sang Wook HAN ,  Young Hun SUNG ,  Hyun Hwa OH

    IPC: G01N23/04

    CPC classification number: G01T7/005 ,  G01T1/169

    Abstract: An X-ray imaging apparatus includes an X-ray generator configured to generate and emit X-rays, an X-ray detector configured to detect the X-rays and count a number of photons having energy equal to or greater than threshold energy per pixel among photons contained in the detected X-rays, a map generator configured to extract corrected threshold energy corresponding to target threshold energy mapped to each pixel, and a data correction unit configured to calculate corrected X-ray data corresponding to the corrected threshold energy per pixel from a plurality of X-ray data acquired based on a plurality of images of a target object obtained by using a plurality of approximate energies equal or approximate to the target threshold energy as threshold energy of the X-ray detector.

    Abstract translation: X射线成像装置包括被配置为产生和发射X射线的X射线发生器，被配置为检测X射线并计数具有等于或大于每像素阈值能量的能量的数量的X光检测器的X射线检测器 在包含在所检测的X射线中的光子之间，映射发生器被配置为提取对应于映射到每个像素的目标阈值能量的校正阈值能量;以及数据校正单元，被配置为计算对应于每像素校正的阈值能量的校正的X射线数据 从基于通过使用等于或近似于目标阈值能量的多个近似能量获得的目标对象的多个图像获取的多个X射线数据作为X射线检测器的阈值能量。

    TIME-TO-DIGITAL CONVERTER AND DIGITAL PHASE-LOCKED LOOP CIRCUIT COMPRISING THE SAME
    3.
    发明公开
    TIME-TO-DIGITAL CONVERTER AND DIGITAL PHASE-LOCKED LOOP CIRCUIT COMPRISING THE SAME 审中-公开

    公开(公告)号：US20230163768A1

    公开(公告)日：2023-05-25

    申请号：US17885844

    申请日：2022-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Min Seob LEE ,  Shin Woong KIM ,  Joon Hee LEE ,  Sang Wook HAN

    IPC: H03L7/099 ,  H03L7/093 ,  H03M1/10

    CPC classification number: H03L7/0992 ,  H03L7/0995 ,  H03L7/093 ,  H03M1/1014

    Abstract: Provided is a time-to-digital converter, comprising a phase frequency detector configured to receive a phase-locked loop input clock and a feedback clock, a ring oscillator configured to perform oscillation with multi-phase clocks of a first period, a counter array configured to count the number of oscillations in which the ring oscillator oscillates in a first period by the number of positive integers during the first pulse width, a multiplexer configured to divide the first period into a plurality of zones using edge information of the multi-phase clocks of the ring oscillator, and selects and outputs voltage information of a plurality of neighboring phase clocks included in a first zone from the plurality of zones, an analog-to-digital converter, a calibrator, and a first adder, wherein the calibrator comprises, an offset lookup table generation circuit, a gain-corrected analog-to-digital conversion output generator, and a second adder.

    RADIO FREQUENCY INTEGRATED CIRCUIT AND COMMUNICATION DEVICE INCLUDING THE INTEGRATED CIRCUIT
    4.
    发明申请
    RADIO FREQUENCY INTEGRATED CIRCUIT AND COMMUNICATION DEVICE INCLUDING THE INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220352921A1

    公开(公告)日：2022-11-03

    申请号：US17588725

    申请日：2022-01-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Woo KIM ,  Jae Min KIM ,  Hyung Gi KIM ,  Sang Wook HAN ,  Ho Rang JANG

    IPC: H04B1/403 ,  H04B7/06

    Abstract: Provided is radio frequency integrated circuit(RFIC). The radio frequency integrated circuit (RFIC) comprises a plurality of transceiver IPs (intellectual property), wherein each transceiver IP includes an analog mixer configured to perform frequency adjustment on a signal input thereto, and a filter configured to perform filtering on the signal having the adjusted frequency based on a predetermined (or alternatively desired) band, a plurality of registers corresponding to the plurality of transceiver IPs, respectively; wherein the plurality of registers are configured to generate a plurality of control signals for controlling the plurality of transceiver IPs, respectively, a memory configured to store therein a plurality of register addresses and a plurality of register data on the plurality of registers, respectively in a form of a lookup table and a processor configured to receive a command related to the lookup table from an external component, and to control the plurality of registers based on the lookup table.

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