公开(公告)号：US10430546B2

公开(公告)日：2019-10-01

申请号：US15802657

申请日：2017-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Sig Won ,  Myung-Soo Jang ,  Hyoun-Soo Park ,  Da-Yeon Cho

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/70

Abstract: A computer-implemented method compresses placing standard cells based on design data defining an integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which a first pattern, a second pattern, and a third pattern in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a non-transitory computer-readable storage medium. The space constraints define minimum spaces between the first pattern, the second pattern, and the third pattern. A color violation does not occur between the first pattern, second pattern, and the third pattern. A first mask, a second mask, and a third mask are generated based on the layout. A semiconductor device is manufactured by using the generated first mask, the second mask, and the third mask.

公开(公告)号：US09135390B2

公开(公告)日：2015-09-15

申请号：US14308741

申请日：2014-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Soo Jang ,  Jae-Rim Lee ,  Jong-Wha Chong ,  Jae-Hwan Kim ,  Byung-Gyu Ahn ,  Cheol-Jon Jang

IPC: G06F17/50 ,  H05K3/00

CPC classification number: G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H05K3/0005

Abstract: To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated. Thus, the numbers of the through-silicon-vias and the power bumps of the power supply network of the semiconductor device are minimal.

Abstract translation: 为了设计采用硅通孔（TSV）技术的3D半导体器件的电源网络，确定了器件的每个板的板布线。 为电路板创建初始网络结构。 产生使用初始网络结构的功率凸起和穿通硅通孔的布局，使得电路板的所有节点的电压都大于参考电压。 制造具有符合布局的板，功率凸起和穿硅通孔的半导体器件。 因此，半导体器件的电源网络的贯通硅通孔和电源突起的数量是最小的。

公开(公告)号：US09026969B2

公开(公告)日：2015-05-05

申请号：US14203650

申请日：2014-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung-Soo Jang ,  Jae-Rim Lee ,  Jong-Wha Chong ,  Min-Beom Kim ,  Wen Rui Li ,  Cheol-Jon Jang

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077

Abstract: A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the TSV candidate grids; determining initial TSV insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final TSV insertion positions by verifying the initial TSV insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability.

Abstract translation: 提供了一种设计堆叠半导体器件中的硅通孔（TSV）布置的方法。该方法包括：确定多个TSV候选栅格，TSV候选栅格表示可插入的多个半导体管芯中相互堆叠的多个半导体管芯中的每一个中的位置 并且包括在堆叠的半导体器件中; 基于所述TSV候选网格，分别创建表示通过所述堆叠半导体器件传输的多个信号的可链接信号路径的多个路径图; 基于路径图确定对应于信号的最短信号路径的初始TSV插入位置; 以及通过验证初始TSV插入位置来确定最终的TSV插入位置，使得对应于信号的最短信号路径的多个信号网络具有可路由性。

公开(公告)号：US20180173838A1

公开(公告)日：2018-06-21

申请号：US15802657

申请日：2017-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Sig Won ,  Myung-Soo Jang ,  Hyoun-Soo Park ,  Da-Yeon Cho

IPC: G06F17/50 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5072

Abstract: A computer-implemented method. Standard cells are placed based on design data defining the integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which first through third patterns in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first through third patterns. A color violation does not occur between the first through third patterns. First, second, and third masks are generated based on the layout. A semiconductor device is manufactured by using the generated first, second, and third masks.

公开(公告)号：US09852256B2

公开(公告)日：2017-12-26

申请号：US14450337

申请日：2014-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Soo Jang ,  Jae-Hwan Kim ,  Cheol-Jon Jang ,  Ji-Ho Song ,  Jong-Wha Chong ,  Kyung-In Cho

IPC: G06F17/50 ,  H01L21/768

CPC classification number: G06F17/5077 ,  H01L21/76898

Abstract: A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die parallel to the first die. The method also includes determining a first bound region. The first bound region includes a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die. The method additionally includes calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.