公开(公告)号：US09852256B2

公开(公告)日：2017-12-26

申请号：US14450337

申请日：2014-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Soo Jang ,  Jae-Hwan Kim ,  Cheol-Jon Jang ,  Ji-Ho Song ,  Jong-Wha Chong ,  Kyung-In Cho

IPC: G06F17/50 ,  H01L21/768

CPC classification number: G06F17/5077 ,  H01L21/76898

Abstract: A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die parallel to the first die. The method also includes determining a first bound region. The first bound region includes a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die. The method additionally includes calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.