公开(公告)号：US20150221746A1

公开(公告)日：2015-08-06

申请号：US14687488

申请日：2015-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuk-soon CHOI ,  Jung-hee LEE ,  Jai-kwang SHIN ,  Jae-joon OH ,  Jong-bong HA ,  Jong-seob KIM ,  In-jun HWANG ,  Ki-ha HONG ,  Ki-sik IM ,  Ki-won KIM ,  Dong-seok KIM

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L29/20 ,  H01L29/201

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/4236 ,  H01L29/7787

Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.

Abstract translation: 所述方法可以包括在衬底上形成第一材料层，增加第一材料层的电阻，以及在第一材料层上形成彼此间隔开的源图案和漏极图案，带隙为 源极和漏极图案大于第一材料层的带隙。

公开(公告)号：US20200152277A1

公开(公告)日：2020-05-14

申请号：US16675914

申请日：2019-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-sun MIN ,  Vivek Venkata KALLURU ,  Tae-hong KWON ,  Ki-won KIM ,  Sung-whan SEO ,  Bilal Ahmad JANJUA

IPC: G11C16/30 ,  H02M3/07 ,  G11C16/10 ,  G11C16/26

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.