公开(公告)号：US20170162276A1

公开(公告)日：2017-06-08

申请号：US15262027

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-ho Ok ,  Pyung-moon Zhang ,  Sang-hoon Shin ,  Ki-hyun Park ,  Yong-sik Park

IPC: G11C29/38 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C29/36 ,  G11C29/50012 ,  G11C2029/3602 ,  G11C2029/5004

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

公开(公告)号：US20160027739A1

公开(公告)日：2016-01-28

申请号：US14736455

申请日：2015-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-hyun Park ,  Byoung-ho KWON ,  Dong-chan KIM ,  Choong-seob SHIN ,  Jong-su KIM ,  Bo-un YOON

IPC: H01L23/544 ,  H01L21/66 ,  H01L21/768 ,  H01L21/4757 ,  H01L21/033

CPC classification number: H01L23/544 ,  H01L21/47573 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L22/12 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.

Abstract translation: 一种制造半导体器件的方法包括在衬底上的第一材料层中形成第一对准标记沟槽。 然后可以通过蚀刻在第一材料层下面的第二材料层来形成第一对准标记通孔，其中第一对准标记通孔被定位成与第一对准标记沟槽连通。 然后，可以通过用光反射材料层填充第一对准标记沟槽和第一对准标记通孔来形成沟槽合并型第一对准标记。

公开(公告)号：US10783979B2

公开(公告)日：2020-09-22

申请号：US16274396

申请日：2019-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-ho Ok ,  Pyung-moon Zhang ,  Sang-hoon Shin ,  Ki-hyun Park ,  Yong-sik Park

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C29/50

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

公开(公告)号：US20190180837A1

公开(公告)日：2019-06-13

申请号：US16274396

申请日：2019-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-ho Ok ,  Pyung-moon Zhang ,  Sang-hoon Shin ,  Ki-hyun Park ,  Yong-sik Park

IPC: G11C29/38 ,  G11C29/50 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C29/36 ,  G11C29/50012 ,  G11C2029/3602 ,  G11C2029/5004

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

公开(公告)号：US10210948B2

公开(公告)日：2019-02-19

申请号：US15262027

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-ho Ok ,  Pyung-moon Zhang ,  Sang-hoon Shin ,  Ki-hyun Park ,  Yong-sik Park

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C29/50

Abstract: A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters and perform a test on at least one memory core. The method includes setting a sweep range including a sweep start point of a first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

公开(公告)号：US09831186B2

公开(公告)日：2017-11-28

申请号：US14736455

申请日：2015-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-hyun Park ,  Byoung-ho Kwon ,  Dong-chan Kim ,  Choong-seob Shin ,  Jong-su Kim ,  Bo-un Yoon

IPC: H01L21/66 ,  H01L23/544 ,  H01L21/4757 ,  H01L21/768

CPC classification number: H01L23/544 ,  H01L21/47573 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L22/12 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.