公开(公告)号：US20230290686A1

公开(公告)日：2023-09-14

申请号：US18061789

申请日：2022-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeojin NA ,  Juyun Park ,  Jongdoo Kim

IPC: H01L21/8234 ,  G06F30/392 ,  G06F30/398

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  G06F30/392 ,  G06F30/398

Abstract: A method of designing a layout of a semiconductor device includes forming a second layout by analyzing a first layout and correcting at least a portion of a plurality of filler cells, wherein the forming the second layout includes detecting transition regions due to a difference in width by respectively comparing a first width of a first active line and a second width of a second active line with a width of a dummy active line, in the first layout; and correcting the dummy active line of the first filler cell by analyzing the detected transition regions, wherein, in the correcting the dummy active line of the first filler cell, the dummy active line is corrected to be a corrected dummy active line having the same width as an active line having a narrower width, among the first and second active lines.

公开(公告)号：US11264482B2

公开(公告)日：2022-03-01

申请号：US16572681

申请日：2019-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Kim ,  Inhyun Song ,  Yeongmin Jeon ,  Sejin Park ,  Juyun Park ,  Jonghoon Baek ,  Taeyeon Shin ,  Sooyeon Jeong

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

Abstract: A semiconductor device may include: a dummy gate structure including a first gate pattern in which dummy gate lines extending in one direction are connected to each other on a substrate, and a second gate pattern in which dummy gate lines extending in the one direction are connected to each other on the same line with the first gate pattern; and a third gate pattern extending in parallel with the dummy gate structure on one side of the dummy gate structure.

公开(公告)号：US20250076749A1

公开(公告)日：2025-03-06

申请号：US18646070

申请日：2024-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeojin NA ,  Jongdoo Kim ,  Juyun Park

IPC: G03F1/36 ,  G03F1/76

Abstract: Provided are an optical proximity correction (OPC) method and a mask manufacturing method including the OPC method for implementing a simulation contour more stiffly to ensure a processing margin. The OPC method includes receiving a design layout for a target pattern, obtaining an OPC pattern by performing first OPC on the design layout, extracting a transition area as an area having a width that changes from a first width to a second width, which is less than the first width, from the target pattern, obtaining a simulation contour for the transition area, calculating at least one of a correction length and a correction angle based on the simulation contour, obtaining a first OPC pattern for the transition area based on at least one of the correction length and the correction angle, and obtaining a final OPC pattern by merging the first OPC pattern with the OPC pattern.