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公开(公告)号：US20240234332A1
公开(公告)日：2024-07-11
申请号：US18489354
申请日：2023-10-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junseok PARK , Seunghak PARK , Chan HWANG
IPC: H01L23/544 , H10B41/27 , H10B43/27
CPC classification number: H01L23/544 , H10B41/27 , H10B43/27 , H01L2223/54426
Abstract: A semiconductor device includes a first stack structure in a first region, a first channel structure in contact with the substrate, a second stack structure on the first stack structure, a second channel structure connected to the first channel structure, a third stack structure on the second stack structure, a third channel structure connected to the second channel structure, a first mold structure in a second region, first overlay structures on the first mold structure, a second mold structure on the first mold structure, second overlay structures on the second mold structure, a third mold structure on the second mold structure, and third overlay structures on the third mold structure, wherein the first to third overlay structures are on an overlay mark region, and the first to third overlay structures are in at least one of quadrants in the overlay mark region.
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公开(公告)号：US20230421946A1
公开(公告)日：2023-12-28
申请号：US18466318
申请日：2023-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junseok PARK , Kyumin KIM , Min LEE
CPC classification number: H04R1/1083 , H04R3/04
Abstract: An electronic device comprising a wireless communication circuit, a microphone, an audio circuit, a processor, and a memory operatively connected to the processor are provided. When a designated application is executed, the electronic device transmits a trigger signal to the audio circuit, transmits the trigger signal to an external electronic device through the wireless communication circuit, acquires a response signal corresponding to the trigger signal by using the microphone from the external electronic device, calculates a path delay time by comparing the trigger signal with the response signal by using the audio circuit, and performs an echo canceling operation based on the path delay time.
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公开(公告)号：US20230236765A1
公开(公告)日：2023-07-27
申请号：US17970628
申请日：2022-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minsik SON , Hyunkoo KIM , Junseok PARK , Suhwan KIM
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0625 , G06F3/0679
Abstract: Disclosed is a method of operating a storage controller which communicates with a host and a non-volatile memory device. The method includes receiving a first state transition request for a device open from the host, performing a first active zone refresh operation of the non-volatile memory device in response to the first state transition request such that a zone, which has an active state before an immediately previous power-off is processed to a sequentially writable state in one block, receiving, by a first buffer memory, first target data to be stored in a first block of a first zone among the plurality of zones from the host depending on a first write request, receiving a first power-off request from the host, during processing the first write request, and storing the first target data in a first power loss protection (PLP) block of the non-volatile memory device.
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4.发明申请NONVOLATILE STORAGE DEVICE AND OPERATING SYSTEM (OS) IMAGE PROGRAM METHOD THEREOF 有权非易失存储器件和操作系统（OS）的图像程序方法公开(公告)号：US20140281170A1
公开(公告)日：2014-09-18
申请号：US14197425
申请日：2014-03-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Hyun CHO , Dongin KIM , Junseok PARK , Taemin LEE , Chaesuk LIM
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0617 , G06F3/0634 , G06F3/0647 , G06F3/0656 , G06F3/0679 , G06F3/0685 , G06F8/63 , G06F11/1008 , G06F12/0246
Abstract: A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area.
Abstract translation: 根据本发明构思的非易失性存储设备包括非易失性存储器件，其包括第一存储区域，第二存储器区域和存储器控制器。 存储器控制器包括被配置为存储可靠模式信息的第一寄存器和被配置为存储操作系统（OS）图像信息的第二寄存器。 存储器控制器被配置为基于可靠模式信息从主机接收命令; 确定该命令是否是针对OS映像的写请求以及伴随命令的OS映像信息是否与存储在第二寄存器中的OS映像信息相匹配; 如果伴随命令的OS图像信息与存储在第二寄存器中的OS图像信息相匹配，并将OS图像从第一存储区块移动到第二存储区域，则将OS图像写入第一存储器区域。
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公开(公告)号：US20200167637A1
公开(公告)日：2020-05-28
申请号：US16675709
申请日：2019-11-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junseok PARK , Inyup KANG
Abstract: An neural network (NN) processor includes an input feature map buffer configured to store an input feature matrix, a weight buffer configured to store a weight matrix trained in a form of a, a transform circuit configured to perform a Walsh-Hadamard transform on an input feature vector obtained from the input feature matrix and a weight vector included in the weight matrix to output a transformed input feature vector and a transformed weight vector, and an arithmetic circuit configured to perform an element-wise multiplication (EWM) on the transformed input feature vector and the transformed weight vector.
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Patent Agency Ranking
公开(公告)号：US20160162212A1
公开(公告)日：2016-06-09
申请号：US15040249
申请日：2016-02-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Hyun CHO , Dongin KIM , Junseok PARK , Taemin LEE , Chaesuk LIM
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0617 , G06F3/0634 , G06F3/0647 , G06F3/0656 , G06F3/0679 , G06F3/0685 , G06F8/63 , G06F11/1008 , G06F12/0246
Abstract: A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area.
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7.发明申请NONVOLATILE STORAGE DEVICE AND OPERATING SYSTEM (OS) IMAGE PROGRAM METHOD THEREOF 审中-公开非易失存储器件和操作系统（OS）的图像程序方法公开(公告)号：US20150106559A1
公开(公告)日：2015-04-16
申请号：US14579810
申请日：2014-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Hyun CHO , Dongin KIM , Junseok PARK , Taemin LEE , Chaesuk LIM
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0617 , G06F3/0634 , G06F3/0647 , G06F3/0656 , G06F3/0679 , G06F3/0685 , G06F8/63 , G06F11/1008 , G06F12/0246
Abstract: A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area.
Abstract translation: 根据本发明构思的非易失性存储设备包括非易失性存储器件，其包括第一存储区域，第二存储器区域和存储器控制器。 存储器控制器包括被配置为存储可靠模式信息的第一寄存器和被配置为存储操作系统（OS）图像信息的第二寄存器。 存储器控制器被配置为基于可靠模式信息从主机接收命令; 确定该命令是否是针对OS映像的写请求以及伴随命令的OS映像信息是否与存储在第二寄存器中的OS映像信息相匹配; 如果伴随命令的OS图像信息与存储在第二寄存器中的OS图像信息相匹配，并将OS图像从第一存储区块移动到第二存储区域，则将OS图像写入第一存储器区域。
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公开(公告)号：US20250077182A1
公开(公告)日：2025-03-06
申请号：US18953922
申请日：2024-11-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinook SONG , Daekyeung KIM , Junseok PARK , Joonho SONG , Sehwan LEE , Junwoo JANG , Yunkyo CHO
Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.
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公开(公告)号：US20240237347A1
公开(公告)日：2024-07-11
申请号：US18380422
申请日：2023-10-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongmin KIM , Seongsoo MOON , SEUNGHAK PARK , Junseok PARK , KI-BONG SEO , Howon SEO , Mingyoo CHOI
Abstract: A method of fabricating a semiconductor device including: alternately stacking first interlayer insulating layers and first sacrificial layers on a substrate to form a first mold structure; forming a dummy hole penetrating the first mold structure; forming a dummy sacrificial pillar in the dummy hole, wherein the formation of the dummy sacrificial pillar includes forming a first recessed key region to expose a portion of an inner side surface of the dummy hole; and forming a second mold structure with a substantially uniform thickness on the first recessed key region and the first mold structure, wherein a top surface of the second mold structure has a second recessed key region corresponding to the first recessed key region.
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公开(公告)号：US20210004264A1
公开(公告)日：2021-01-07
申请号：US16976131
申请日：2019-03-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongchul HWANG , Suyong KIM , Junseok PARK , Jonghwa LEE
Abstract: According to various embodiments of the disclosure, disclosed is an electronic device that includes a display, a memory, and a processor electrically connected to the display and the memory, wherein the processor is configured to receive a first input of a user executing a first application, to execute at least one process for executing the first application in response to the received first input, to acquire first information including an ID and a start time of the executed at least one process, to receive a second input of the user executing a second application, and to display a name of the first application corresponding to the ID on the display in a form of a calendar in response to the received second input, based on the start time. Additional various embodiments identified through the specification are possible.
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