公开(公告)号：US20210174179A1

公开(公告)日：2021-06-10

申请号：US16989391

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinook SONG ,  Daekyeung KIM ,  Junseok PARK ,  Joonho SONG ,  Sehwan LEE ,  Junwoo JANG ,  Yunkyo CHO

IPC: G06N3/063 ,  G06F7/485

Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

公开(公告)号：US20250077182A1

公开(公告)日：2025-03-06

申请号：US18953922

申请日：2024-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinook SONG ,  Daekyeung KIM ,  Junseok PARK ,  Joonho SONG ,  Sehwan LEE ,  Junwoo JANG ,  Yunkyo CHO

IPC: G06F7/544 ,  G06N3/063

Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.