公开(公告)号：US11869751B2

公开(公告)日：2024-01-09

申请号：US18085949

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungjo Kim ,  Sangki Nam ,  Jungmin Ko ,  Kwonsang Seo ,  Seungbo Shim ,  Younghyun Jo

IPC: H01J37/32

CPC classification number: H01J37/32541 ,  H01J37/32642 ,  H01J37/32715

Abstract: An upper electrode used for a substrate processing apparatus using plasma is provided. The upper electrode includes a bottom surface including a center region and an edge region having a ring shape and surrounding the center region, a first protrusion portion protruding toward plasma from the edge region and having a ring shape, wherein the first protrusion portion includes a first apex corresponding to a radial local maximum point toward the plasma, and a first distance, which is a radial-direction distance between the first apex and a center axis of the upper electrode, is greater than a radius of a substrate.

公开(公告)号：US11545344B2

公开(公告)日：2023-01-03

申请号：US17188064

申请日：2021-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungjo Kim ,  Sangki Nam ,  Jungmin Ko ,  Kwonsang Seo ,  Seungbo Shim ,  Younghyun Jo

IPC: H01J37/32

Abstract: An upper electrode used for a substrate processing apparatus using plasma is provided. The upper electrode includes a bottom surface including a center region and an edge region having a ring shape and surrounding the center region, a first protrusion portion protruding toward plasma from the edge region and having a ring shape, wherein the first protrusion portion includes a first apex corresponding to a radial local maximum point toward the plasma, and a first distance, which is a radial-direction distance between the first apex and a center axis of the upper electrode, is greater than a radius of a substrate.

公开(公告)号：US11469099B2

公开(公告)日：2022-10-11

申请号：US16905310

申请日：2020-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Ko ,  Hyeongmun Kang ,  Sangsick Park ,  Hyeonjun Song

IPC: G11C5/06 ,  H01L27/108 ,  H01L21/02 ,  H01L21/56 ,  H01L21/762

Abstract: A semiconductor package includes a buffer, a chip stack mounted on the buffer, an adhesive layer disposed between the buffer and the chip stack, and a molding material surrounding the chip stack. The buffer includes a plurality of trenches disposed adjacent to a plurality of edges of the buffer. Each of the trenches is shorter than a corresponding adjacent edge of a chip area of the buffer.

公开(公告)号：US20250105193A1

公开(公告)日：2025-03-27

申请号：US18890118

申请日：2024-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Ko ,  Hyunhee Lee ,  Hojun Lee ,  Dongjoo Choi

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a first semiconductor chip including a first through-via and a first upper pad, a second semiconductor chip provided on the first semiconductor chip and including a second lower pad, and a bonding bump provided between the first semiconductor chip and the second semiconductor chip and connected to the first upper pad and the second lower pad. The bonding bump includes: a conductive pattern directly contacting the second lower pad and including nickel and a bonding structure directly contacting the conductive pattern and the first upper pad, wherein the bonding structure includes an intermetallic compound including copper and a solder material. A thickness of the bonding structure is from about 47% to about 54% of a sum of a thickness of the conductive pattern, a thickness of the bonding structure, and a thickness of the first upper pad.

公开(公告)号：US12154881B2

公开(公告)日：2024-11-26

申请号：US18185702

申请日：2023-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae Cho ,  Jinyeol Yang ,  Jungmin Ko ,  Seungduk Baek

IPC: H01L23/00 ,  H01L25/065

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

公开(公告)号：US20210143008A1

公开(公告)日：2021-05-13

申请号：US16905310

申请日：2020-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Ko ,  Hyeongmun Kang ,  Sangsick Park ,  Hyeonjun Song

IPC: H01L21/02 ,  H01L21/56 ,  H01L21/762

Abstract: A semiconductor package includes a buffer, a chip stack mounted on the buffer, an adhesive layer disposed between the buffer and the chip stack, and a molding material surrounding the chip stack. The buffer includes a plurality of trenches disposed adjacent to a plurality of edges of the buffer. Each of the trenches is shorter than a corresponding adjacent edge of a chip area of the buffer.

公开(公告)号：US11721601B2

公开(公告)日：2023-08-08

申请号：US17095210

申请日：2020-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeongmun Kang ,  Jungmin Ko ,  Seungduk Baek ,  Taehyeong Kim ,  Insup Shin

IPC: H01L23/24 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/24 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/5385 ,  H01L24/13 ,  H01L2924/1434 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and molding resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from side surfaces of the molding resin.

公开(公告)号：US11658160B2

公开(公告)日：2023-05-23

申请号：US17574953

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjun Song ,  Eunkyul Oh ,  Hyeongmun Kang ,  Jungmin Ko

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4871 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L24/14 ,  H01L25/50 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2224/14519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other.

公开(公告)号：US11756935B2

公开(公告)日：2023-09-12

申请号：US17352757

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Insup Shin ,  Hyeongmun Kang ,  Jungmin Ko ,  Hwanyoung Choi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.

公开(公告)号：US20230223374A1

公开(公告)日：2023-07-13

申请号：US18185702

申请日：2023-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae CHO ,  Jinyeol Yang ,  Jungmin Ko ,  Seungduk Baek

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/20 ,  H01L25/0655 ,  H01L24/05 ,  H01L24/29 ,  H01L24/13 ,  H01L2224/29009 ,  H01L2224/13083 ,  H01L2224/0557 ,  H01L2224/29008 ,  H01L2924/14 ,  H01L2224/0401

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.