公开(公告)号：US20170371250A1

公开(公告)日：2017-12-28

申请号：US15481204

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Lim KIM ,  Jong-Doo KIM ,  Joong-Won JEON

IPC: G03F7/20 ,  H01L21/8234 ,  G03F1/26 ,  H01L29/66 ,  H01L21/66

CPC classification number: G03F7/70625 ,  G03F1/26 ,  G03F1/36 ,  G03F1/44 ,  G03F1/84 ,  G03F7/70683 ,  H01L21/823431 ,  H01L22/12 ,  H01L22/30 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: Methods of inspecting photomasks are provided. A method of inspecting a photomask includes electronically inspecting a first mask pattern in a mask region of the photomask and refraining from electronically inspecting a separate second mask pattern in the mask region of the photomask. The first mask pattern includes a geometric feature that corresponds to at least a portion of the second mask pattern. Moreover, the mask region is outside of a scribe lane region of the photomask. Related methods of manufacturing photomasks and methods of manufacturing semiconductor devices are also provided.

公开(公告)号：US20170069533A1

公开(公告)日：2017-03-09

申请号：US15236427

申请日：2016-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Doo KIM ,  Joong-Won JEON ,  Young-Deok KWON ,  Suk-Joo LEE

IPC: H01L21/768 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L21/823475 ,  H01L21/76804 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207

Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes forming an interlayer insulating layer that comprises a first region and a second region, forming an etch stop pattern for exposing the second region in the first region of the interlayer insulating layer and forming a mask pattern that comprises a first via-hole that exposes an upper surface of the etch stop pattern and a second via-hole that penetrates the interlayer insulating layer on the interlayer insulating layer and the etch stop pattern.

Abstract translation: 提供一种制造半导体器件的方法。 制造半导体器件的方法包括形成包括第一区域和第二区域的层间绝缘层，形成用于暴露层间绝缘层的第一区域中的第二区域的蚀刻停止图案，并形成掩模图案，掩模图案包括 暴露蚀刻停止图案的上表面的第一通孔和穿过层间绝缘层和蚀刻停止图案上的层间绝缘层的第二通孔。

公开(公告)号：US20150143312A1

公开(公告)日：2015-05-21

申请号：US14449377

申请日：2014-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joong-Won JEON ,  Ji-Youn SONG ,  Mun-Su SHIN ,  Seong-Yul PARK ,  Suk-Joo LEE

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/70 ,  G03F7/70433

Abstract: A method of designing patterns of semiconductor devices includes forming a plurality of tiles having patterns on a wafer, measuring the patterns of the plurality of tiles, analyzing the measurements of the patterns and determining a tile having such a size that the measurements linearly vary according to a design size and pattern density, and modifying the pattern density of the determined tile.

Abstract translation: 一种设计半导体器件图形的方法包括：在晶片上形成具有图案的多个瓦片，测量多个瓦片的图案，分析图案的测量结果，以及确定具有这样的尺寸的瓦片，使得测量值根据 设计尺寸和图案密度，以及修改确定的瓷砖的图案密度。

公开(公告)号：US20130320405A1

公开(公告)日：2013-12-05

申请号：US13785156

申请日：2013-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joong-Won JEON ,  Hee-Sung KANG ,  Dae-Ho YOON ,  Dal-Hee LEE ,  Suk-Joo LEE

IPC: H01L27/02

CPC classification number: H01L27/0207 ,  H01L29/94

Abstract: A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.

Abstract translation: 半导体器件包括布置在半导体器件的中心区域中的逻辑区域和设置在其外部区域中的周边区域。 逻辑区域包括线形逻辑晶体管和盒形去耦电容器。 周边区域包括线形外围晶体管和与外围晶体管相邻设置的线状外围虚拟晶体管。