公开(公告)号：US20230309312A1

公开(公告)日：2023-09-28

申请号：US18299150

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park ,  Kwang Soo Kim

IPC: H10B43/40 ,  H01L23/535 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/535 ,  H10B43/27

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

公开(公告)号：US11094708B2

公开(公告)日：2021-08-17

申请号：US16378625

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/423 ,  H01L23/48 ,  H01L21/28 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11519

Abstract: A vertical-type memory device includes a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure, a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, and a plurality of gate contact plugs penetrating the interlayer insulating layer and respectively in contact with the gate electrode layers. The plurality of gate electrode layers include lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers, so that the lower gate electrodes are between the substrate and the upper gate electrode layers. The plurality of gate contact plugs include lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers. The upper gate contact plugs have top-most portions disposed at a height higher than a height of top surfaces of the lower gate contact plugs.

公开(公告)号：US11145669B2

公开(公告)日：2021-10-12

申请号：US16451385

申请日：2019-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park ,  Kwang Soo Kim

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11582

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

公开(公告)号：US12004353B2

公开(公告)日：2024-06-04

申请号：US18299150

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park ,  Kwang Soo Kim

IPC: H10B43/40 ,  H01L23/535 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/535 ,  H10B43/27

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

公开(公告)号：US11765900B2

公开(公告)日：2023-09-19

申请号：US17398455

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/48 ,  H10B43/27 ,  H01L29/423 ,  H01L21/28 ,  H10B43/10 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40

CPC classification number: H10B43/27 ,  H01L23/481 ,  H01L29/40117 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40

Abstract: A vertical-type memory device includes a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure, a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, and a plurality of gate contact plugs penetrating the interlayer insulating layer and respectively in contact with the gate electrode layers. The plurality of gate electrode layers include lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers, so that the lower gate electrodes are between the substrate and the upper gate electrode layers. The plurality of gate contact plugs include lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers. The upper gate contact plugs have top-most portions disposed at a height higher than a height of top surfaces of the lower gate contact plugs.

公开(公告)号：US20220028878A1

公开(公告)日：2022-01-27

申请号：US17495320

申请日：2021-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park ,  Kwang Soo Kim

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11582

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

公开(公告)号：US11659713B2

公开(公告)日：2023-05-23

申请号：US17495320

申请日：2021-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park ,  Kwang Soo Kim

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11582

CPC classification number: H01L27/11573 ,  H01L23/535 ,  H01L27/11582

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

公开(公告)号：US20200185400A1

公开(公告)日：2020-06-11

申请号：US16451385

申请日：2019-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won Park ,  Kyeong Jin Park ,  Kwang Soo Kim

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L23/535

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.