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Patent Agency Ranking
公开(公告)号：US11011233B2
公开(公告)日：2021-05-18
申请号：US16442670
申请日：2019-06-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Jin Kim , Sang-Ryong Park , Jong-Nam Baek , Sejeong Jang
Abstract: A nonvolatile memory device includes a memory cell array that includes memory blocks, wherein each of the memory blocks includes pages each including memory cells, a row decoder circuit that selects one of the pages from a selected memory block of the memory blocks in a write operation and selects memory cells of a close unit from the selected memory block in a close operation, and a page buffer circuit that writes data into memory cells of a page selected by the row decoder circuit in the write operation and writes dummy data into the memory cells of the close unit selected by the row decoder circuit in the close operation. The close unit includes one or more pages, and, in the close operation, the row decoder circuit adjusts a size of the close unit.
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公开(公告)号：US09606864B2
公开(公告)日：2017-03-28
申请号：US13947219
申请日：2013-07-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung-Yeon Lee , Hee-Woong Kang , Jong-Nam Baek , San Song
CPC classification number: G06F11/1068 , G11C11/5642 , G11C16/26 , G11C16/3431
Abstract: A nonvolatile memory device includes a memory cell array including a selected page including multiple error correction code (ECC) units, and a voltage generation unit configured to generate a read voltage to read data from the selected page. Read voltage levels are set individually for the respective ECC units according to data detection results for each of the ECC units. During a read retry section performed with respect to selected ECC units of the selected page for which read errors have been detected, a re-read operation of the selected ECC units is performed according to the respective read voltage levels set for the selected ECC units.
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3.发明授权Memory system including nonvolatile memory devices which contain multiple page buffers and control logic therein that support varying read voltage level test operations 有权存储系统包括包含多页缓冲器和其中的控制逻辑的非易失性存储器件，其支持不同的读电压电平测试操作公开(公告)号：US09396796B2
公开(公告)日：2016-07-19
申请号：US14525768
申请日：2014-10-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang Hoon Lee , Hyun Seok Kim , Sung-Hwan Bae , Jong-Nam Baek , Jae Yong Jeong
CPC classification number: G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/26 , G11C29/00
Abstract: A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device.
Abstract translation: 非易失性存储器件包括非易失性存储器单元的阵列和多个页缓冲器，其被配置为使用不同的读取电压条件从阵列中的同一页面接收多页数据。 提供了一种控制电路，其电耦合到多个页面缓冲器。 控制电路被配置为通过用控制信号驱动多个页面缓冲器来执行测试操作，该控制信号导致非易失性存储器件内的异或数据位串的产生，这是从多个页面中的至少两个的比较导出的 使用不同的读取电压条件从同一页的非易失性存储单元读取数据。 提供了一种输入/输出设备，其被配置为将从XOR数据位串导出的测试数据输出到位于非易失性存储器件外部的另一个设备。
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4.发明申请NON-VOLATILE MEMORY, METHOD OF OPERATING THE SAME, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE SYSTEM 审中-公开非易失性存储器，其操作方法，包括其的存储器系统以及操作系统的方法公开(公告)号：US20150070997A1
公开(公告)日：2015-03-12
申请号：US14525768
申请日：2014-10-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang Hoon Lee , Hyun Seok Kim , Sung-Hwan Bae , Jong-Nam Baek , Jae Yong Jeong
CPC classification number: G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/26 , G11C29/00
Abstract: A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device.
Abstract translation: 非易失性存储器件包括非易失性存储器单元的阵列和多个页缓冲器，其被配置为使用不同的读取电压条件从阵列中的同一页面接收多页数据。 提供了一种控制电路，其电耦合到多个页面缓冲器。 控制电路被配置为通过用控制信号驱动多个页面缓冲器来执行测试操作，该控制信号导致非易失性存储器件内的异或数据位串的产生，这是从多个页面中的至少两个的比较导出的 使用不同的读取电压条件从同一页的非易失性存储单元读取数据。 提供了一种输入/输出设备，其被配置为将从XOR数据位串导出的测试数据输出到位于非易失性存储器件外部的另一个设备。
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公开(公告)号：US09190155B2
公开(公告)日：2015-11-17
申请号：US14155960
申请日：2014-01-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Joon-Ho Lee , Jong-Nam Baek , Dong-Hoon Ham , Sang-Wook Yoo , In-Tae Hwang
CPC classification number: G11C16/16 , G11C16/0483
Abstract: A memory system includes a flash memory including a block having first sub-blocks and second sub-blocks different from each other, the second sub-blocks including free pages only; and a controller configured to erase the flash memory in units of the sub-blocks, and in a garbage collection operation, the controller is configured to copy data of a valid page of the first sub-blocks to at least one of the second sub-blocks.
Abstract translation: 存储器系统包括闪存，其包括具有彼此不同的第一子块和第二子块的块，第二子块仅包括空闲页; 以及控制器，被配置为以子块为单位擦除闪速存储器，并且在垃圾收集操作中，控制器被配置为将第一子块的有效页面的数据复制到第二子块中的至少一个， 块。
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