公开(公告)号：US20230170296A1

公开(公告)日：2023-06-01

申请号：US17961056

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anthony Dongick LEE ,  Sangcheol NA ,  Kichul PARK ,  Doohwan PARK ,  Kyoungwoo LEE ,  Rakhwan KIM ,  Yoonsuk KIM ,  Jinnam KIM ,  Hoonjoo NA ,  Eunji JUNG ,  Juyoung JUNG

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/53238 ,  H01L23/53223 ,  H01L23/53266

Abstract: A semiconductor device includes a substrate. A wiring layer is over the substrate. A first via structure directly contacts a lower portion of the wiring layer. A second via structure directly contacts an upper portion of the wiring layer. The first via structure generates first stress in the wiring layer. The second via structure generates second stress in the wiring layer. The second stress is of an opposite type to the first stress. The first stress and the second stress compensate for each other in the wiring layer.

公开(公告)号：US20220093567A1

公开(公告)日：2022-03-24

申请号：US17376784

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam KIM ,  Seokho KIM ,  Hoonjoo NA ,  Kwangjin MOON

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a first structure including a first semiconductor chip, and a second structure on the first structure. The second structure includes a second semiconductor chip, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern.

公开(公告)号：US20240234377A9

公开(公告)日：2024-07-11

申请号：US18536332

申请日：2023-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinnam KIM ,  Seokho KIM ,  Hoonjoo NA ,  Kwangjin MOON

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06541

Abstract: A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.

公开(公告)号：US20240136334A1

公开(公告)日：2024-04-25

申请号：US18536332

申请日：2023-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinnam KIM ,  Seokho KIM ,  Hoonjoo NA ,  Kwangjin MOON

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06541

Abstract: A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.

公开(公告)号：US20140080302A1

公开(公告)日：2014-03-20

申请号：US13966345

申请日：2013-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tsukasa MATSUDA ,  Jinnam KIM ,  Jongho YUN ,  Jongmyeong LEE

IPC: H01L21/768

CPC classification number: H01L21/76883 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885

Abstract: A method of manufacturing a semiconductor device including forming a first sacrificial layer on a substrate, the first sacrificial layer including a conductive material, forming a second sacrificial layer on the first sacrificial layer, the second sacrificial layer including an insulating material, patterning the second sacrificial layer and the first sacrificial layer to form an opening successively penetrating the second and first sacrificial layers, conformally forming a seed layer on the second and first sacrificial layers including the opening, and forming a conductive pattern filling the opening having the seed layer by a plating process.

Abstract translation: 一种制造半导体器件的方法，包括在衬底上形成第一牺牲层，所述第一牺牲层包括导电材料，在所述第一牺牲层上形成第二牺牲层，所述第二牺牲层包括绝缘材料，图案化所述第二牺牲层 层和第一牺牲层，以形成连续穿过第二和第一牺牲层的开口，在包括开口的第二和第一牺牲层上保形地形成晶种层，并且通过电镀形成填充具有晶种层的开口的导电图案 处理。

公开(公告)号：US20240266257A1

公开(公告)日：2024-08-08

申请号：US18382545

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin LIM ,  Jinnam KIM ,  Jongmin BAEK ,  Hyoseok CHOI

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate having a front surface including an active region and a rear surface opposite to the front surface. An active pattern is on the active region. A gate structure extends in a second direction on the active region. Source/drain regions are disposed on the active pattern on both sides of the gate structure. A front interconnection structure is disposed on the gate structure and the source/drain regions. A rear interconnection structure is disposed on the rear surface of the substrate. A target region defined by the source/drain regions and the active pattern includes a non-oxidizing material at a first concentration. The non-oxidizing material is injected during a high-pressure heat treatment process. A rear interconnection region defined by the substrate, the rear through-structure, and the rear interconnection structure includes the non-oxidizing material at a second concentration higher than the first concentration.