公开(公告)号：US20190272885A1

公开(公告)日：2019-09-05

申请号：US16417834

申请日：2019-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-Ho KIM ,  Jihwan YU ,  Seunghyun CHO

IPC: G11C19/28 ,  G11C11/412 ,  G11C8/14 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565

Abstract: Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

公开(公告)号：US20230171965A1

公开(公告)日：2023-06-01

申请号：US18070789

申请日：2022-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin LEE ,  Kwanyong KIM ,  Jihwan YU

IPC: H10B43/40 ,  H10B41/35 ,  H01L23/528 ,  H10B41/40 ,  H10B41/27 ,  H10B43/35 ,  H10B43/27

CPC classification number: H01L27/11573 ,  H01L27/11524 ,  H01L23/5283 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device including a stack structure including gate stack and dummy stack regions; a vertical memory structure penetrating through the gate stack region; and a first vertical dummy structure penetrating through a portion of the dummy stack region, wherein the gate stack region includes interlayer insulating and gate layers alternately and repeatedly stacked on each other, the dummy stack region includes dummy insulating and dummy horizontal layers alternately and repeatedly stacked on each other, at least one of the dummy horizontal layers and the gate layers include materials different from each other, an upper surface of the vertical memory structure is at a higher level than an upper surface of the first vertical dummy structure, and a lowermost dummy upper horizontal layer at a higher level than the first vertical dummy structure overlaps the first vertical dummy structure.