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公开(公告)号:US20140124854A1
公开(公告)日:2014-05-08
申请号:US14154740
申请日:2014-01-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Heedon Hwang , Ji-Young Min , Jongchul Park , Insang Jeon , Woogwan Shim
CPC classification number: H01L29/7827 , H01L27/10876 , H01L27/228 , H01L27/2436 , H01L29/66666 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146
Abstract: Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include a trench in a substrate. The semiconductor devices may also include a bulk electrode within opposing sidewalls of the trench. The semiconductor devices may further include a liner electrode between the bulk electrode and the opposing sidewalls of the trench. The liner electrode may include a sidewall portion between a sidewall of the bulk electrode and one of the opposing sidewalls of the trench.
Abstract translation: 可以提供半导体器件及其形成方法。 半导体器件可以在衬底中包括沟槽。 半导体器件还可以包括在沟槽的相对侧壁内的体电极。 半导体器件还可以包括在本体电极和沟槽的相对侧壁之间的衬垫电极。 衬里电极可以包括在本体电极的侧壁和沟槽的相对侧壁中的一个之间的侧壁部分。
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公开(公告)号:US20140035058A1
公开(公告)日:2014-02-06
申请号:US13940440
申请日:2013-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ji-Young Min , Gab-Jin Nam , Eun-Ae Chung , Jung-Dal Choi , Jin-Soak Kim , Sung-Kweon Baek
IPC: H01L27/092 , H01L21/8234
CPC classification number: H01L27/092 , H01L21/823437 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857
Abstract: Methods of manufacturing a semiconductor device include forming a thin layer on a substrate including a first region and a second region and forming a gate insulating layer on the thin layer. A lower electrode layer is formed on the gate insulating layer and the lower electrode layer disposed in the second region is removed to expose the gate insulating layer in the second region. Nitrogen is doped into an exposed portion of the gate insulating layer and the thin layer disposed under the gate insulating layer. An upper electrode layer is formed on the lower electrode layer remaining in the first region and the exposed portion of the gate insulating layer. The upper electrode layer, the lower electrode layer, the gate insulating layer and the thin layer are partially removed to form first and second gate structures in the first and second regions. The process may be simplified.
Abstract translation: 制造半导体器件的方法包括在包括第一区域和第二区域的衬底上形成薄层,并在薄层上形成栅绝缘层。 在栅极绝缘层上形成下部电极层,去除设置在第二区域中的下部电极层,露出第二区域的栅极绝缘层。 将氮掺杂到栅极绝缘层的暴露部分和设置在栅极绝缘层下方的薄层。 在保持在第一区域中的下电极层和栅绝缘层的露出部分上形成上电极层。 部分去除上电极层,下电极层,栅极绝缘层和薄层,以在第一和第二区域中形成第一和第二栅极结构。 该过程可以被简化。
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公开(公告)号:US09368589B2
公开(公告)日:2016-06-14
申请号:US14167053
申请日:2014-01-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung-Kweon Baek , Gab-Jin Nam , Jin-Soak Kim , Ji-Young Min , Eun-Ae Chung
IPC: H01L29/66 , H01L21/336 , H01L29/423 , H01L29/78 , H01L27/108
CPC classification number: H01L29/4236 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L29/7827
Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.
Abstract translation: 半导体器件包括设置在半导体衬底的有源区中的第一源极/漏极区域和第二源极/漏极区域以及与有源区域交叉并设置在第一和第二源极/漏极区域之间的栅极结构,栅极结构 包括在第一部分具有第一部分和第二部分的栅电极,栅电极处于比有源区的上表面更低的电平,栅电极上的绝缘封盖图案,栅电极之间的栅极电介质 和有源区,以及有源区和栅电极的第二部分之间的空白空间。
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公开(公告)号:US09064957B2
公开(公告)日:2015-06-23
申请号:US14154740
申请日:2014-01-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Heedon Hwang , Ji-Young Min , Jongchul Park , Insang Jeon , Woogwan Shim
CPC classification number: H01L29/7827 , H01L27/10876 , H01L27/228 , H01L27/2436 , H01L29/66666 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146
Abstract: Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include a trench in a substrate. The semiconductor devices may also include a bulk electrode within opposing sidewalls of the trench. The semiconductor devices may further include a liner electrode between the bulk electrode and the opposing sidewalls of the trench. The liner electrode may include a sidewall portion between a sidewall of the bulk electrode and one of the opposing sidewalls of the trench.
Abstract translation: 可以提供半导体器件及其形成方法。 半导体器件可以在衬底中包括沟槽。 半导体器件还可以包括在沟槽的相对侧壁内的体电极。 半导体器件还可以包括在本体电极和沟槽的相对侧壁之间的衬垫电极。 衬里电极可以包括在本体电极的侧壁和沟槽的相对侧壁中的一个之间的侧壁部分。
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