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    ANTENNA SYSTEM FOR TRANSMITTING AND RECEIVING MM-WAVE SIGNAL
    1.
    发明申请
    ANTENNA SYSTEM FOR TRANSMITTING AND RECEIVING MM-WAVE SIGNAL 有权

    公开(公告)号：US20220216589A1

    公开(公告)日：2022-07-07

    申请号：US17693501

    申请日：2022-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Hoon KIM ,  Ji Yong KIM ,  Jong In LEE ,  Yeon Jeong KIM ,  Yong Jun AN ,  Hyo Seok NA

    IPC: H01Q1/22 ,  H01Q23/00 ,  H01Q21/00 ,  H01Q1/24 ,  H01Q9/04 ,  H01L23/66 ,  H01P5/18 ,  H01Q5/335 ,  H01Q21/06

    Abstract: Disclosed in an electronic device, which includes a housing that includes a first plate and a second plate facing a direction opposite the first plate, a conductive plate that is disposed in a first plane between the first plate and the second plate, and is parallel to the second plate, a wireless communication circuit that is disposed within the housing and is configured to transmit and/or receive a signal having a frequency ranging from 20 GHz to 100 GHz, a first electrical path having a first end electrically connected with the wireless communication circuit and a second end floated, the first electrical path including a first portion between the first end and the second end, a second electrical path having a third end electrically connected with the conductive plate and a fourth end floated, the second electrical path including a second portion between the third end and the fourth end.

    METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE
    2.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220028837A1

    公开(公告)日：2022-01-27

    申请号：US17493975

    申请日：2021-10-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Hwan HWANG ,  Ji Hoon KIM ,  Ji Seok HONG ,  Tae Hun KIM ,  Hyuek Jae LEE

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

    Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

    ANTENNA SYSTEM FOR TRANSMITTING AND RECEIVING MM-WAVE SIGNAL
    4.
    发明申请
    ANTENNA SYSTEM FOR TRANSMITTING AND RECEIVING MM-WAVE SIGNAL 审中-公开

    公开(公告)号：US20190165449A1

    公开(公告)日：2019-05-30

    申请号：US16202596

    申请日：2018-11-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Hoon KIM ,  Ji Yong KIM ,  Jong In LEE ,  Yeon Jeong KIM ,  Yong Jun AN ,  Hyo Seok NA

    IPC: H01Q1/22 ,  H01Q1/24 ,  H01Q21/00 ,  H01Q23/00

    Abstract: Disclosed in an electronic device, which includes a housing that includes a first plate and a second plate facing a direction opposite the first plate, a conductive plate that is disposed in a first plane between the first plate and the second plate, and is parallel to the second plate, a wireless communication circuit that is disposed within the housing and is configured to transmit and/or receive a signal having a frequency ranging from 20 GHz to 100 GHz, a first electrical path having a first end electrically connected with the wireless communication circuit and a second end floated, the first electrical path including a first portion between the first end and the second end, a second electrical path having a third end electrically connected with the conductive plate and a fourth end floated, the second electrical path including a second portion between the third end and the fourth end.

    METHOD AND APPARATUS FOR PROVIDING CHARACTER INPUT INTERFACE
    5.
    发明申请
    METHOD AND APPARATUS FOR PROVIDING CHARACTER INPUT INTERFACE 审中-公开
    用于提供字符输入接口的方法和装置

    公开(公告)号：US20160062650A1

    公开(公告)日：2016-03-03

    申请号：US14935997

    申请日：2015-11-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Wook PARK ,  Se Hwan PARK ,  Ji Hoon KIM ,  Ji Hoon LEE

    IPC: G06F3/0488 ,  G06F3/01 ,  G06F3/0484

    CPC classification number: G06F3/04886 ,  G06F3/018 ,  G06F3/0238 ,  G06F3/04847 ,  G06F3/04883

    Abstract: A method and an apparatus are provided for providing a character input interface in a terminal having a touchscreen. A single keyboard is displayed in a keyboard area of the touchscreen. A first keyboard and a second keyboard are simultaneously displayed in place of the single keyboard in the keyboard area, upon detecting selection of a key on the single keyboard. At least one of the first keyboard and the second keyboard includes a plurality of character-type selection keys, and at least one of the plurality of character-type selection keys includes a language selection key. A controlling unit of the terminal changes a type of characters displayed on one of the first keyboard and the second keyboard, upon detecting selection of one of the plurality of character-type selection keys on the one of the first keyboard and the second keyboard.

    Abstract translation: 提供了一种用于在具有触摸屏的终端中提供字符输入接口的方法和装置。 单键盘显示在触摸屏的键盘区域。 在检测到单键盘上的键的选择时，第一键盘和第二键盘代替键盘区域中的单个键盘同时显示。 第一键盘和第二键盘中的至少一个包括多个字符型选择键，并且多个字符型选择键中的至少一个包括语言选择键。 在检测到在第一键盘和第二键盘之一上选择多个字符型选择键中的一个时，终端的控制单元改变显示在第一键盘和第二键盘之一上的字符的类型。

    STORAGE DEVICE AND MEMORY SYSTEM
    7.
    发明申请
    STORAGE DEVICE AND MEMORY SYSTEM 有权

    公开(公告)号：US20230072613A1

    公开(公告)日：2023-03-09

    申请号：US17696586

    申请日：2022-03-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Soo Young JI ,  Joo Young KIM ,  Ji Hoon KIM ,  Jae Young DO ,  Yeo Reum PARK

    IPC: G06F3/06

    Abstract: A storage device is provided. The storage device includes a controller which receives a command from a host for instructing performance of a first computation, a non-volatile memory which stores a plurality of datasets, a buffer memory to which a first dataset among the plurality of datasets stored in the non-volatile memory is provided in response to the command, and an accelerator which performs the first computation corresponding to the command, using the first dataset provided to the buffer memory. The accelerator includes a memory access module which receives a first input query for instructing the first computation and the first dataset from the buffer memory, and a first computing module which is connected to the memory access module and determines first final candidate data corresponding to the first input query, using the first dataset.

    NEURAL NETWORK DEVICE INCLUDING CONVOLUTION SRAM AND DIAGONAL ACCUMULATION SRAM
    10.
    发明申请
    NEURAL NETWORK DEVICE INCLUDING CONVOLUTION SRAM AND DIAGONAL ACCUMULATION SRAM 有权

    公开(公告)号：US20220207334A1

    公开(公告)日：2022-06-30

    申请号：US17459921

    申请日：2021-08-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Suk Han LEE ,  Joo-Young KIM ,  Kyo Min SOHN ,  Ji Hoon KIM ,  Jae Hoon HEO

    IPC: G06N3/063 ,  G11C11/412 ,  G11C11/419 ,  G11C11/54 ,  G11C11/418

    Abstract: A neural network device including a convolution static random access memory (SRAM) configured to output a first operation value and a second operation value 1. An accumulation peripheral operator configured to perform an accumulation peripheral operation on the first and the second operation values, a multiplexer array configured to select and output an output value according to a selection signal, a diagonal accumulation SRAM configured to perform a bitwise accumulation of variable weight values and a spatial-wise accumulation operation on an input, a diagonal movement logic, and an addition array operator configured to perform an addition operation of output values of the diagonal movement logic subsequent to a shift operation, the multiplexer array selects any one of an output value of the accumulation peripheral operator and an output value of the addition array operator according to the selection signal and outputs the selected output value to the diagonal accumulation SRAM.

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