公开(公告)号：US20200210190A1

公开(公告)日：2020-07-02

申请号：US16374743

申请日：2019-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan J. HENSLEY ,  Fuzhou ZOU ,  Monika TKACZYK ,  Eric C. QUINNELL ,  James David DUNDAS ,  Madhu Saravana Sibi GOVINDAN

IPC: G06F9/38 ,  G06F9/30

Abstract: According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.

公开(公告)号：US20190235873A1

公开(公告)日：2019-08-01

申请号：US16019502

申请日：2018-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： James David DUNDAS ,  Gerald David ZURASKI, Jr. ,  Karthik SUNDARAM

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F12/0875 ,  G06F2212/452

Abstract: According to one general aspect, an apparatus may include a front end logic section comprising a main-branch target buffer (BTB). The apparatus may also include a micro-BTB separate from the main BTB, and configured to produce prediction information associated with a branching instruction and mark prediction information as verified when one or more conditions are satisfied. Wherein the front end logic section is configured to be, at least partially, powered down when the data stored by the micro-BTB that results in the prediction information is marked as previously verified.

公开(公告)号：US20200371944A1

公开(公告)日：2020-11-26

申请号：US16578257

申请日：2019-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： James David DUNDAS

IPC: G06F12/0875

Abstract: Micro-operations (μops) are allocated into a μop cache by dividing, by a micro branch target buffer (μBTB), instructions into a first basic block in which the instructions are executed by a processing device and the first basic block corresponds to an edge of the instructions being executed by the processing device. The μBTB allocates the first basic block to an inverted basic block queue (IBBQ) and the IBBQ determines that the first basic block fits into the μop cache. The IBBQ allocates the first basic block to the μop cache based on a number of times the edge of the instructions corresponding to the first basic block is repeatedly executed by the processing device.