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公开(公告)号：US20180081630A1
公开(公告)日：2018-03-22
申请号：US15809971
申请日：2017-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eric C. QUINNELL
CPC classification number: G06F7/485 , G06F7/49915 , G06F7/49936 , G06F7/50
Abstract: According to one general aspect, an apparatus may include a floating-point addition unit that includes a far path circuit, a close path circuit, and a final result selector circuit. The far path circuit may be configured to compute a far path result based upon either the addition or the subtraction of the two floating-point numbers regardless of whether the operands or the result include normal or denormal numbers. The close path circuit may be configured to compute a close path result based upon the subtraction of the two floating-point operands regardless of whether the operands or the result include normal or denormal numbers. The final result selector circuit may be configured to select between the far path result and the close path result based, at least in part, upon an amount of difference in the exponent portions of the two floating-point operands.
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Patent Agency Ranking
公开(公告)号：US20200210190A1
公开(公告)日：2020-07-02
申请号：US16374743
申请日：2019-04-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ryan J. HENSLEY , Fuzhou ZOU , Monika TKACZYK , Eric C. QUINNELL , James David DUNDAS , Madhu Saravana Sibi GOVINDAN
Abstract: According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.
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公开(公告)号：US20180181392A1
公开(公告)日：2018-06-28
申请号：US15901873
申请日：2018-02-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eric C. QUINNELL
IPC: G06F9/30
CPC classification number: G06F9/30014 , G06F9/30036
Abstract: According to one general aspect, an apparatus may include a monolithic shifter configured to receive a plurality of bytes of data, and, for each byte of data, a number of bits to shift the respective byte of data, wherein the number of bits for each byte of data need not be the same as for any other byte of data. The monolithic shifter may be configured to shift each byte of data by the respective number of bits. The apparatus may include a mask generator configured to compute a mask for each byte of data, wherein each mask indicates which bits, if any, are to be prevented from being polluted by a neighboring shifted byte of data. The apparatus may include a masking circuit configured to combine the shifted byte of data with a respective mask to create an unpolluted shifted byte of data.
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公开(公告)号：US20170010893A1
公开(公告)日：2017-01-12
申请号：US14856538
申请日：2015-09-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eric C. QUINNELL
IPC: G06F9/30
CPC classification number: G06F9/30014 , G06F9/30036
Abstract: According to one general aspect, an apparatus may include a monolithic shifter configured to receive a plurality of bytes of data, and, for each byte of data, a number of bits to shift the respective byte of data, wherein the number of bits for each byte of data need not be the same as for any other byte of data. The monolithic shifter may be configured to shift each byte of data by the respective number of bits. The apparatus may include a mask generator configured to compute a mask for each byte of data, wherein each mask indicates which bits, if any, are to be prevented from being polluted by a neighboring shifted byte of data. The apparatus may include a masking circuit configured to combine the shifted byte of data with a respective mask to create an unpolluted shifted byte of data.
Abstract translation: 根据一个一般方面，一种装置可以包括：单片移位器，被配置为接收多个字节的数据，并且对于数据的每个字节，移位数据的各个字节的位数，其中每个数据的位数 数据字节不需要与任何其他数据字节相同。 单片移位器可以被配置为将数据的每个字节移位相应的位数。 该设备可以包括掩模发生器，其被配置为针对每个数据字节计算掩码，其中每个掩码指示要防止哪些位被数据的相邻移位字节污染。 该装置可以包括掩蔽电路，其被配置为将数据的移位字节与相应的掩码组合，以产生未被污染的数据移位字节。
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5.发明申请公开(公告)号：US20200210626A1
公开(公告)日：2020-07-02
申请号：US16283725
申请日：2019-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Monika TKACZYK , Brian C. GRAYSON , Mohamad Basem BARAKAT , Eric C. QUINNELL , Bradley G. BURGESS
Abstract: According to one general aspect, an apparatus may include a context-specific encryption key circuit configured to generate a key value, wherein the key value is specific to a context of a set of instructions. The apparatus may include a target address prediction circuit configured to provide a target address for a next instruction in the set of instructions. The apparatus may include a target address memory configured to store an encrypted version of the target address, wherein the target address is encrypted using, at least in part, the key value. The apparatus may further include an instruction fetch circuit configured to decrypt the target address using, at least in part, the key value, and retrieve the target address.
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公开(公告)号：US20180276140A1
公开(公告)日：2018-09-27
申请号：US15616917
申请日：2017-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eric C. QUINNELL , Kevin C. HEUER , Tarun NAKRA , Akhil ARUNKUMAR
IPC: G06F12/123 , G06F12/0891 , G06F12/0815 , G06F12/0862
CPC classification number: G06F12/123 , G06F12/0815 , G06F12/0862 , G06F12/0891 , G06F2212/602 , G06F2212/621
Abstract: Embodiments of the present system and method provide cache replacement in a victim exclusive cache using a snoop filter where replacement information is not lost during a re-reference back to the CPU. Replacement information is stored in a snoop filter, meaning that historical access data may be fully preserved and allows for more flexibility in the LLC re-insertion points, without additional bits stored in a L2 cache. The present system and method further include snoop filter replacement technique. The present system and method passes replacement information between a snoop filter and a victim exclusive cache (e.g., LLC) when transactions move cachelines to and from a master CPU. This maintains and advances existing replacement information for a cacheline that is removed from the victim exclusive cache on a read, as well as intelligently replaces and ages cachelines in the snoop filter.
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