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    Computing system including CXL switch, memory device and storage device and operating method thereof
    5.
    发明授权
    Computing system including CXL switch, memory device and storage device and operating method thereof 有权

    公开(公告)号：US12287751B2

    公开(公告)日：2025-04-29

    申请号：US18131185

    申请日：2023-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghan Lee ,  Jae-gon Lee ,  Chon Yong Lee

    IPC: G06F13/42 ,  G06F12/02 ,  G06F13/16

    Abstract: A computing system includes a first storage device, a second storage device, a memory device, and a compute express link (CXL) switch. The memory device stores first map data of the first storage device and second map data of the second storage device. The CXL switch is connected with the first storage device, the second storage device, and an external host through a first interface, and arbitrates communications between the first storage device, the second storage device, and the external host. The first storage device is connected with the memory device through a second interface. The second storage device is connected with the memory device through a third interface. The first interface, the second interface, and the third interface are physically separated from each other.

    SYSTEM ON CHIP INCLUDING CLOCK MANAGEMENT UNIT AND METHOD OF OPERATING THE SYSTEM ON CHIP
    7.
    发明申请
    SYSTEM ON CHIP INCLUDING CLOCK MANAGEMENT UNIT AND METHOD OF OPERATING THE SYSTEM ON CHIP 审中-公开
    芯片系统，包括时钟管理单元和操作系统的芯片方法

    公开(公告)号：US20160350259A1

    公开(公告)日：2016-12-01

    申请号：US15156825

    申请日：2016-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ho-yeon JEON ,  Jae-gon Lee ,  Youn-sik Choi ,  Min-joung Lee ,  Jin-ook Song

    IPC: G06F13/42 ,  G06F13/364

    CPC classification number: G06F13/4291 ,  G06F13/364

    Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

    Abstract translation: 在一个实施例中，时钟管理电路包括第一主时钟控制器，其被配置为基于接收的第一时钟请求经由第一信道向第一从时钟控制器提供第一命令。 时钟管理电路还包括配置成基于第一命令控制输出第一时钟信号的第一从时钟控制器。

    System-on-chip for providing access to shared memory via chip-to-chip link, operation method of the same, and electronic system including the same
    8.
    发明授权
    System-on-chip for providing access to shared memory via chip-to-chip link, operation method of the same, and electronic system including the same 有权
    片上系统，用于通过芯片到芯片链路提供对共享存储器的访问，其操作方法以及包括其的电子系统

    公开(公告)号：US09146880B2

    公开(公告)日：2015-09-29

    申请号：US13895606

    申请日：2013-05-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-hun Heo ,  Jae-youl Kim ,  Jae-gon Lee ,  Nam-phil Jo

    IPC: G06F12/14 ,  G06F13/16 ,  G06F3/06 ,  G06F1/32

    CPC classification number: G06F12/14 ,  G06F1/3253 ,  G06F1/3275 ,  G06F3/0655 ,  G06F13/1663 ,  G06F13/1668 ,  G06F2213/0038 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D50/20

    Abstract: An electronic system including a system-on-chip (SoC) providing access to a shared memory via a chip-to-chip link includes a memory device, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first central processing unit (CPU) and a memory access path configured to enable access to the memory device. The second semiconductor device is configured to access the memory device via the memory access path of the first semiconductor device. The second semiconductor device is permitted to access the memory device while the memory access path is active and the first CPU is inactive, and the memory access path is configured to become active without intervention of the first CPU.

    Abstract translation: 包括通过芯片到芯片链路提供对共享存储器的访问的片上系统（SoC）的电子系统包括存储器件，第一半导体器件和第二半导体器件。 第一半导体器件包括第一中央处理单元（CPU）和被配置为使得能够访问存储器件的存储器访问路径。 第二半导体器件被配置为经由第一半导体器件的存储器访问路径访问存储器件。 允许第二半导体器件访问存储器件，同时存储器访问路径被激活并且第一CPU不活动，并且存储器访问路径被配置为在没有第一CPU的干预的情况下变为活动状态。

    SYSTEM-ON-CHIP FOR PROVIDING ACCESS TO SHARED MEMORY VIA CHIP-TO-CHIP LINK, OPERATION METHOD OF THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAME
    9.
    发明申请
    SYSTEM-ON-CHIP FOR PROVIDING ACCESS TO SHARED MEMORY VIA CHIP-TO-CHIP LINK, OPERATION METHOD OF THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权
    通过芯片到芯片链路提供对共享存储器的访问的系统芯片，其操作方法和包括其的电子系统

    公开(公告)号：US20130318311A1

    公开(公告)日：2013-11-28

    申请号：US13895606

    申请日：2013-05-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JUNG-HUN HEO ,  Jae-youl Kim ,  Jae-gon Lee ,  Nam-phil Jo

    IPC: G06F12/14

    CPC classification number: G06F12/14 ,  G06F1/3253 ,  G06F1/3275 ,  G06F3/0655 ,  G06F13/1663 ,  G06F13/1668 ,  G06F2213/0038 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D50/20

    Abstract: An electronic system including a system-on-chip (SoC) providing access to a shared memory via a chip-to-chip link includes a memory device, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first central processing unit (CPU) and a memory access path configured to enable access to the memory device. The second semiconductor device is configured to access the memory device via the memory access path of the first semiconductor device. The second semiconductor device is permitted to access the memory device while the memory access path is active and the first CPU is inactive, and the memory access path is configured to become active without intervention of the first CPU.

    Abstract translation: 包括通过芯片到芯片链路提供对共享存储器的访问的片上系统（SoC）的电子系统包括存储器件，第一半导体器件和第二半导体器件。 第一半导体器件包括第一中央处理单元（CPU）和被配置为使得能够访问存储器件的存储器访问路径。 第二半导体器件被配置为经由第一半导体器件的存储器访问路径访问存储器件。 允许第二半导体器件访问存储器件，同时存储器访问路径被激活并且第一CPU不活动，并且存储器访问路径被配置为在没有第一CPU的干预的情况下变为活动状态。

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