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公开(公告)号：US12213322B2
公开(公告)日：2025-01-28
申请号：US17380331
申请日：2021-07-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwan Lee , Kwang Seok Kim , Yong Seok Kim , Il Gweon Kim , Kil Ho Lee
Abstract: A three-dimensional semiconductor memory device is provided. The semiconductor memory device includes first horizontal conductive lines on a substrate in a first direction, each of the first horizontal conductive lines extending in a second direction different from the first direction, second horizontal conductive lines stacked on the substrate in the first direction, each of the second horizontal conductive lines extending in the second direction, a vertical conductive line between the first horizontal conductive line and the second horizontal conductive line and extending in the first direction, a plurality of first magnetic tunnel junction patterns between the vertical conductive line and each of the first horizontal conductive lines, and a plurality of second magnetic tunnel junction patterns between the vertical conductive lines and each of the second horizontal conductive lines. The first horizontal conductive lines and the second horizontal conductive lines are spaced apart from each other in a third direction.
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公开(公告)号：US12048150B2
公开(公告)日：2024-07-23
申请号：US17377848
申请日：2021-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwan Lee , Yong Seok Kim , Il Gweon Kim , Hyun Cheol Kim , Hyeoung Won Seo , Sung Won Yoo , Jae Ho Hong
Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.
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公开(公告)号：US11903184B2
公开(公告)日：2024-02-13
申请号：US17392488
申请日：2021-08-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwan Lee , Yong Seok Kim , Il Gweon Kim , Hui-Jung Kim , Min Hee Cho , Jae Ho Hong
IPC: H01L27/108 , H01L29/24 , H10B12/00 , G11C11/402
CPC classification number: H10B12/34 , G11C11/4023 , H01L29/24
Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.
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公开(公告)号：US20220199625A1
公开(公告)日：2022-06-23
申请号：US17392488
申请日：2021-08-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Hwan Lee , Yong Seok Kim , Il Gweon Kim , Hui-Jung Kim , Min Hee Cho , Jae Ho Hong
IPC: H01L27/108 , G11C11/402 , H01L29/24
Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.
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