公开(公告)号：US20240313049A1

公开(公告)日：2024-09-19

申请号：US18394926

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon KIM ,  Hyunwoong KIM ,  Sungsik PARK ,  Jonghwa BAEK ,  KyungMin SUH ,  Hyunju SONG ,  Myoungki JUNG

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate having a key region therein, a device isolation layer on the key region, first key patterns on the device isolation layer, and a dummy key pattern extending between the first key patterns, which are adjacent to each other. The first key patterns include a plurality of first sub-key patterns, and the dummy key pattern includes a separation structure, which extends into the device isolation layer and through at least one of the plurality of first sub-key patterns. A first pitch between the plurality of first sub-key patterns may be substantially the same as a second pitch between the separation structure and one of the plurality of first sub-key patterns adjacent thereto.

公开(公告)号：US20240332221A1

公开(公告)日：2024-10-03

申请号：US18422406

申请日：2024-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoung AHN ,  Seonghi LEE ,  Hyunwoong KIM ,  Jiseong KIM

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/64 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1435

Abstract: A semiconductor package includes a package substrate, an interposer die disposed on the package substrate, semiconductor chips disposed on the interposer die and electrically connected to the package substrate via the interposer die, first connection bumps electrically connecting the semiconductor chips to the interposer die, second connection bumps electrically connecting the interposer die to the package substrate, and third connection bumps disposed below the package substrate, wherein the interposer die includes spiral matching structures adjacent to upper portions of the second connection bumps, and the package substrate includes trace-shaped matching structures adjacent to lower portions of the second connection bumps.