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    Semiconductor device having chip ID generation circuit
    2.
    发明授权
    Semiconductor device having chip ID generation circuit 有权

    公开(公告)号：US10319451B2

    公开(公告)日：2019-06-11

    申请号：US15232586

    申请日：2016-08-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yang-gyoon Loh ,  Je-min Ryu ,  Hyun-ki Kim ,  Yoon-jae Jeong

    IPC: G06F11/00 ,  G11C17/18 ,  G11C17/16 ,  G11C29/12 ,  G11C29/00 ,  G06F11/16 ,  G11C8/12 ,  G11C29/44

    Abstract: Provided is a semiconductor device including chip identification (ID) generation circuits. The semiconductor device may be a multi-chip package including a plurality of memory chips, and each of the memory chips includes a chip ID generation circuit configured to selectively modify a chip ID of a corresponding memory chip. The chip ID generation circuit determines the chip ID of the memory chip by testing the chip ID of the memory chip by using a mode register, and selectively programs the chip ID of the memory chip by using at least two fuse sets. The chip ID generation circuit may block an output of the chip ID of the memory chip when the memory chip is determined as a defective chip or is selected to stop its use.

    Semiconductor package
    6.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US10699983B2

    公开(公告)日：2020-06-30

    申请号：US16190825

    申请日：2018-11-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kil-soo Kim ,  Yong-hoon Kim ,  Hyun-ki Kim ,  Kyung-suk Oh

    IPC: H01L23/433 ,  H01L23/60 ,  H01L25/065 ,  H01L23/373 ,  H01L23/367 ,  H01L23/552 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.

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