公开(公告)号：US20200303374A1

公开(公告)日：2020-09-24

申请号：US16894045

申请日：2020-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deepak SHARMA ,  Hyun-jong LEE ,  Raheel AZMAT ,  Chul-hong PARK ,  Sang-jun PARK

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

公开(公告)号：US20200294999A1

公开(公告)日：2020-09-17

申请号：US16887331

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deepak SHARMA ,  Hyun-jong LEE ,  Raheel AZMAT ,  Chul-hong PARK ,  Sang-jun PARK

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

公开(公告)号：US20170033101A1

公开(公告)日：2017-02-02

申请号：US15060829

申请日：2016-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deepak SHARMA ,  Hyun-jong LEE ,  Raheel AZMAT ,  Chul-hong PARK ,  Sang-jun PARK

IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/6681

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

Abstract translation: 提供了包括至少一个单元的集成电路，所述至少一个单元包括彼此间隔开的第一和第二有源区，设置在第一和第二有源区之间的虚拟区，设置在第一和第二有源区中的至少一个第一有源鳍 有源区并且在第一方向上延伸，在第二有源区的整个长度上沿着第一方向延伸的至少一个第二有源鳍，以及沿基本上垂直于第一方向的第二方向延伸的有源栅极线，其中 有源栅极线垂直地与第一有源区和虚拟区重叠，并且不垂直地与第二有源区重叠。