-
公开(公告)号:US10199355B2
公开(公告)日:2019-02-05
申请号:US15358579
申请日:2016-11-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Donghyun Kim , DooWon Kwon
IPC: H01L25/065 , H01L23/00 , H01L27/146 , F01P7/04 , F01P11/20
Abstract: A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.
-
公开(公告)号:US09711554B2
公开(公告)日:2017-07-18
申请号:US14958987
申请日:2015-12-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: DooWon Kwon , Taeseok Oh
IPC: H01L27/146
CPC classification number: H01L27/14636 , H01L27/14612 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14634 , H01L27/1464 , H01L27/1469 , H01L2924/0002 , H01L2924/00
Abstract: An image sensor includes a pixel array chip, a logic chip, and an interposed layer. The interposed layer is disposed on the pixel array chip. The logic chip is disposed on the interposed layer. The interposed layer includes a connecting part, a shielding part, and a metal-diffusion barrier layer. The connecting part electrically connects a first interconnection wire of the pixel array chip and a second interconnection wire of the logic chip. The connecting part includes a first metallic element. The shielding part is disposed spatially apart from the connecting part and electrically grounded to suppress an electrical coupling between the pixel array chip and the logic chip. The shielding part includes a second metallic element. The metal-diffusion barrier layer is disposed on top and bottom surfaces of the interposed layer to limit diffusion of electrical charges to the pixel array chip and the logic chip.
-
公开(公告)号:US20170154873A1
公开(公告)日:2017-06-01
申请号:US15358579
申请日:2016-11-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Donghyun Kim , DooWon Kwon
IPC: H01L25/065 , H01L23/00 , H01L27/146
CPC classification number: H01L25/0657 , B60H1/00764 , B60H1/00828 , B60H1/321 , B60H2001/3248 , B60H2001/3258 , B60K11/06 , F01P7/048 , F01P11/20 , F01P2050/24 , H01L24/02 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14643 , H01L2224/02331 , H01L2224/16014 , H01L2224/16145 , H01L2224/17106 , H01L2224/32012 , H01L2224/32145 , H01L2224/48091 , H01L2224/73203 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2225/06565 , H01L2924/00014
Abstract: A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.
-
公开(公告)号:US10483243B2
公开(公告)日:2019-11-19
申请号:US16236882
申请日:2018-12-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Donghyun Kim , DooWon Kwon
IPC: H01L25/065 , H01L23/00 , H01L27/146 , B60K11/06 , B60H1/00 , B60H1/32 , F01P7/04 , F01P11/20
Abstract: A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.
-
公开(公告)号:US20190157245A1
公开(公告)日:2019-05-23
申请号:US16236882
申请日:2018-12-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Donghyun Kim , DooWon Kwon
IPC: H01L25/065 , B60H1/00 , H01L27/146 , H01L23/00 , B60H1/32 , B60K11/06
Abstract: A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.
-
-
-
-