公开(公告)号：US11011511B2

公开(公告)日：2021-05-18

申请号：US16167117

申请日：2018-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Lim Kang ,  Hyun-Jo Kim ,  Jong-Mil Youn ,  Soo-Hun Hong

IPC: H01L27/02 ,  H01L29/16 ,  H01L29/08 ,  H01L27/088 ,  H01L29/78 ,  H01L21/02

Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.

公开(公告)号：US12074157B2

公开(公告)日：2024-08-27

申请号：US17320477

申请日：2021-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Lim Kang ,  Hyun-Jo Kim ,  Jong-Mil Youn ,  Soo-Hun Hong

IPC: H01L27/02 ,  H01L21/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L21/02293 ,  H01L27/0248 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/7831 ,  H01L29/785

Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.

公开(公告)号：US09496192B2

公开(公告)日：2016-11-15

申请号：US14326471

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Lim Kang ,  Min-Ho Kwon ,  Wei-Hua Hsu ,  Sang-Hyun Woo ,  Hwa-Sung Rhee ,  Jun-Suk Choi

IPC: H01L27/088 ,  H01L21/66

CPC classification number: H01L22/34 ,  H01L27/0886

Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.

Abstract translation: 提供了一种半导体器件的测试图案，其包括形成为从衬底突出并布置成彼此间隔开的第一和第二鳍片，分别形成为跨越第一和第二鳍片的第一和第二栅极结构，第一和第二鳍片 源极区域和布置在第一鳍片的第一栅极结构的一侧和另一侧上的第一漏极区域，在第二栅极的一侧和另一侧上布置在第二鳍片上的第二源极区域和第二漏极区域 结构，连接到第一和第二漏极区域以将第一电压施加到第一和第二漏极区域的第一导电图案以及将第一源极区域和第二栅极结构彼此连接的第二导电图案。