公开(公告)号：US11309326B2

公开(公告)日：2022-04-19

申请号：US16832389

申请日：2020-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jo-young Park ,  Chang-seok Kang ,  Chang-sup Lee ,  Se-mee Jang

IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L21/768

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

公开(公告)号：US10658374B2

公开(公告)日：2020-05-19

申请号：US16416319

申请日：2019-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jo-young Park ,  Chang-seok Kang ,  Chang-sup Lee ,  Se-mee Jang

IPC: H01L27/115 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L21/768

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

公开(公告)号：US20190279999A1

公开(公告)日：2019-09-12

申请号：US16416319

申请日：2019-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jo-young Park ,  Chang-seok Kang ,  Chang-sup Lee ,  Se-mee Jang

IPC: H01L27/11575 ,  H01L27/11548

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

公开(公告)号：US20200227430A1

公开(公告)日：2020-07-16

申请号：US16832389

申请日：2020-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jo-young Park ,  Chang-seok Kang ,  Chang-sup Lee ,  Se-mee Jang

IPC: H01L27/11575 ,  H01L27/11548

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

公开(公告)号：US10297543B2

公开(公告)日：2019-05-21

申请号：US15620870

申请日：2017-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jo-young Park ,  Chang-seok Kang ,  Chang-sup Lee ,  Se-mee Jang

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

公开(公告)号：US09299446B2

公开(公告)日：2016-03-29

申请号：US14303741

申请日：2014-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-hyung Kim ,  Chang-seok Kang ,  Young-suk Kim

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C2216/18

Abstract: A nonvolatile memory device includes: a plurality of cell strings disposed on a substrate, wherein at least one of the plurality of cell strings comprises a plurality of cell transistors and at least one ground select transistor stacked in a direction substantially perpendicular to the substrate, and the substrate and a channel region of the plurality of cell strings have a same conductivity type; a substrate bias circuit configured to provide an erase voltage to the substrate in an erase operation; and a ground select line voltage generator configured to provide a ground select line saturation voltage to the at least one ground select transistor in the erase operation.

Abstract translation: 非易失性存储器件包括：设置在衬底上的多个单元串，其中所述多个单元串中的至少一个包括多个单元晶体管和至少一个基本上垂直于所述衬底的方向堆叠的接地选择晶体管，以及 所述基板和所述多个电池串的沟道区域具有相同的导电类型; 衬底偏置电路，被配置为在擦除操作中向所述衬底提供擦除电压; 以及接地选择线电压发生器，被配置为在所述擦除操作中向所述至少一个接地选择晶体管提供接地选择线饱和电压。