公开(公告)号：USRE50225E1

公开(公告)日：2024-11-26

申请号：US17668441

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shin-Hwan Kang ,  Young-Hwan Son ,  Dong-seog Eun ,  Chang-sup Lee ,  Jae-hoon Jang

IPC: H10B43/50 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.

公开(公告)号：US20200227430A1

公开(公告)日：2020-07-16

申请号：US16832389

申请日：2020-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jo-young Park ,  Chang-seok Kang ,  Chang-sup Lee ,  Se-mee Jang

IPC: H01L27/11575 ,  H01L27/11548

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

公开(公告)号：US10297543B2

公开(公告)日：2019-05-21

申请号：US15620870

申请日：2017-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jo-young Park ,  Chang-seok Kang ,  Chang-sup Lee ,  Se-mee Jang

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

公开(公告)号：US11309326B2

公开(公告)日：2022-04-19

申请号：US16832389

申请日：2020-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jo-young Park ,  Chang-seok Kang ,  Chang-sup Lee ,  Se-mee Jang

IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L21/768

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

公开(公告)号：US10886289B2

公开(公告)日：2021-01-05

申请号：US15946432

申请日：2018-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shin-hwan Kang ,  Young-hwan Son ,  Dong-seog Eun ,  Chang-sup Lee ,  Jae-hoon Jang

IPC: H01L27/11556 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.

公开(公告)号：US10658374B2

公开(公告)日：2020-05-19

申请号：US16416319

申请日：2019-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jo-young Park ,  Chang-seok Kang ,  Chang-sup Lee ,  Se-mee Jang

IPC: H01L27/115 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L21/768

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.

公开(公告)号：US20190279999A1

公开(公告)日：2019-09-12

申请号：US16416319

申请日：2019-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jo-young Park ,  Chang-seok Kang ,  Chang-sup Lee ,  Se-mee Jang

IPC: H01L27/11575 ,  H01L27/11548

Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.