公开(公告)号：US11889692B2

公开(公告)日：2024-01-30

申请号：US17349193

申请日：2021-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Min Choi ,  Ju-Young Lim ,  Su-Jin Ahn

IPC: H01L27/06 ,  H10B43/27 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L23/528

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L27/0688 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

公开(公告)号：US10283204B2

公开(公告)日：2019-05-07

申请号：US15607551

申请日：2017-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Min Choi ,  Dong-Chan Kim ,  Ae-Jeong Lee ,  Moo-Rym Choi

IPC: G06F12/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/22 ,  G11C16/34

Abstract: In a method of operating a nonvolatile memory device, a first sub-block to be erased is selected in a first memory block including the first sub-block and a second sub-block adjacent to the first sub-block, in response to a erase command and an address. The first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line. An erase voltage is applied to a substrate in which the first memory block is formed. Based on a voltage level of the erase voltage applied to the substrate, applying, a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block.

公开(公告)号：US10242997B2

公开(公告)日：2019-03-26

申请号：US15223255

申请日：2016-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Min Choi ,  Ju-Young Lim ,  Su-Jin Ahn

IPC: H01L27/108 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/06 ,  H01L27/11578 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11575

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.