公开(公告)号：US20160150355A1

公开(公告)日：2016-05-26

申请号：US14899286

申请日：2014-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Sik YOO ,  Byung-soo KIM ,  Seul-A KIM ,  Chan-Won KIM ,  Seung-Yeon EOM ,  Doo-Man LEE ,  Han-Vit CHUNG ,  Seung-Jin CHOI

IPC: H04W4/00

CPC classification number: H04W4/80 ,  G06F3/017 ,  H04L65/1083 ,  H04M1/7253 ,  H04M1/72563 ,  H04M2250/02 ,  H04M2250/04 ,  H04M2250/12

Abstract: A method of controlling an operation mode of an electronic device and the electronic device therefore are provided. The method includes verifying an operation mode of the first electronic device when it is verified that a second electronic device is approached within a predetermined range while transmitting and receiving data with a third electronic device and changing a first mode to a second mode when the first electronic device operates in the first mode.

Abstract translation: 因此，提供了一种控制电子设备和电子设备的操作模式的方法。 该方法包括：当第一电子设备在第一电子设备被发现和接收数据的同时，在第三电子设备发送和接收数据并且将第一模式改变为第二模式时，验证第一电子设备的操作模式， 设备在第一模式下工作。

公开(公告)号：US20150364366A1

公开(公告)日：2015-12-17

申请号：US14673169

申请日：2015-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Won KIM ,  Jung-Woo Seo

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L49/02 ,  H01L21/311 ,  H01L21/56 ,  H01L21/033

CPC classification number: H01L21/76877 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/3135 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L28/40 ,  H01L28/91

Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.

Abstract translation: 提供了形成能够实现具有高纵横比的电极的硬掩模的方法。 可以在基板上形成成型层。 可以在模制层上形成牺牲层。 可以在牺牲层中平行地形成第一掩模图案。 在形成第一掩模图案之后，可以在牺牲层中形成穿过第一掩模图案并且平行的第二掩模图案。 第一掩模图案和第二掩模图案可以具有比牺牲层更不透明的材料。 牺牲层的上表面，第一掩模图案和第二掩模图案可以以相同的水平面曝光。 牺牲层可以被去除。 通过成型层的开口可以使用第一掩模图案和第二掩模图案作为蚀刻掩模来形成。 电极可以形成在开口中。

公开(公告)号：US20150079791A1

公开(公告)日：2015-03-19

申请号：US14326960

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjoon PARK ,  Junho YOON ,  Je-Woo HAN ,  Chan-Won KIM

IPC: H01L21/308 ,  H01L49/02

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/31144 ,  H01L23/544 ,  H01L28/40 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayered insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayered insulating layer, forming trenches in the first mask layer exposing the interlayered insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayered insulating layer may be greater than that of the key mask patterns with respect to the interlayered insulating layer.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括在具有单元区域和外围电路区域的结构上形成层间绝缘层，在层间绝缘层上形成第一掩模层，在第一掩模层中形成通过图案化第一掩模 并且在沟槽中形成键掩模图案。 第一掩模图案相对于层间绝缘层的蚀刻选择性可以大于关于键层掩模图案相对于层间绝缘层的蚀刻选择性。