公开(公告)号：US20180323209A1

公开(公告)日：2018-11-08

申请号：US16021295

申请日：2018-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGHYUN LEE ,  CHANJIN PARK ,  BYOUNGKEUN SON ,  SUNG-IL CHANG

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/0649 ,  H01L29/7926

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

公开(公告)号：US20180019258A1

公开(公告)日：2018-01-18

申请号：US15676011

申请日：2017-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANGHYUN LEE ,  BYOUNGKEUN SON

IPC: G11C16/04 ,  H01L23/50 ,  H01L21/28

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/0483 ,  H01L21/28008 ,  H01L23/50 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/00 ,  H01L2924/0002

Abstract: Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other.

公开(公告)号：US20200152659A1

公开(公告)日：2020-05-14

申请号：US16739417

申请日：2020-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGHYUN LEE ,  CHANJIN PARK ,  BYOUNGKEUN SON ,  SUNG-IL CHANG

IPC: H01L27/11582 ,  H01L27/11551 ,  H01L29/792 ,  H01L29/06 ,  H01L27/11578 ,  H01L27/11556

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

公开(公告)号：US20180151590A1

公开(公告)日：2018-05-31

申请号：US15871375

申请日：2018-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANGHYUN LEE ,  Byoungkeun Son ,  Hyejin Cho

IPC: H01L27/11582 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7926

Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

公开(公告)号：US20150214243A1

公开(公告)日：2015-07-30

申请号：US14682111

申请日：2015-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANGHYUN LEE ,  BYOUNGKEUN SON

IPC: H01L27/115 ,  H01L23/50 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/0483 ,  H01L21/28008 ,  H01L23/50 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/00 ,  H01L2924/0002

Abstract: Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other.

Abstract translation: 提供了非易失性存储器件及其形成方法。 非易失性存储器件包括多个字线，接地选择线，串选择线和虚拟字线。 虚拟字线和接地选择线之间以及虚拟字线和字线之间的距离中的每一个都大于彼此相邻的一对字线之间的距离。

公开(公告)号：US20140104945A1

公开(公告)日：2014-04-17

申请号：US14135049

申请日：2013-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGHYUN LEE ,  BYOUNGKEUN SON

IPC: G11C16/04 ,  H01L21/28

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/0483 ,  H01L21/28008 ,  H01L23/50 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/00 ,  H01L2924/0002

Abstract: Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other.

Abstract translation: 提供了非易失性存储器件及其形成方法。 非易失性存储器件包括多个字线，接地选择线，串选择线和虚拟字线。 虚拟字线和接地选择线之间以及虚拟字线和字线之间的距离中的每一个都大于彼此相邻的一对字线之间的距离。