公开(公告)号：US10475501B2

公开(公告)日：2019-11-12

申请号：US15946992

申请日：2018-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Yeon Jeon ,  Ah Chan Kim ,  Min Joung Lee ,  Youn-Sik Choi

IPC: G11C7/10 ,  G11C11/34 ,  H03M9/00 ,  G06F13/28 ,  G06F11/34

Abstract: A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured.

公开(公告)号：US10296065B2

公开(公告)日：2019-05-21

申请号：US15414969

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Gon Lee ,  Ah Chan Kim ,  Jin Ook Song ,  Jae Young Lee ,  Youn Sik Choi

IPC: G06F1/00 ,  G06F1/3234 ,  G06F13/42 ,  G06F1/06 ,  H04J3/06 ,  H04J3/14 ,  H04L12/933

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

公开(公告)号：US10248155B2

公开(公告)日：2019-04-02

申请号：US15415041

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Hun Kim ,  Ah Chan Kim ,  Youn Sik Choi ,  Jae Gon Lee

IPC: G06F1/00 ,  H04L5/00 ,  G06F1/06 ,  G06F1/3237

Abstract: A semiconductor device includes a first clock generating circuit including a first control circuit and a first clock gating circuit, a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method, a second clock generating circuit including a second control circuit and a second clock gating circuit, and a second channel management circuit which communicates with the second clock generating circuit according to the full handshake method. The first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock.

公开(公告)号：US11314278B2

公开(公告)日：2022-04-26

申请号：US17154373

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Yeon Jeon ,  Ah Chan Kim ,  Jae Gon Lee

IPC: G06F1/10 ,  G06F1/32 ,  G06F1/3237

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

公开(公告)号：US20210141412A1

公开(公告)日：2021-05-13

申请号：US17154373

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HO YEON JEON ,  Ah Chan Kim ,  Jae Gon Lee

IPC: G06F1/10 ,  G06F1/3237

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

公开(公告)号：US10928849B2

公开(公告)日：2021-02-23

申请号：US16393106

申请日：2019-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Yeon Jeon ,  Ah Chan Kim ,  Jae Gon Lee

IPC: G06F1/10 ,  G06F1/32 ,  G06F1/3237

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

公开(公告)号：US10969854B2

公开(公告)日：2021-04-06

申请号：US16416600

申请日：2019-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Gon Lee ,  Ah Chan Kim ,  Jin Ook Song ,  Jae Young Lee ,  Youn Sik Choi

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/06 ,  G06F13/42 ,  H04J3/06 ,  H04J3/14 ,  H04L12/933 ,  G06F1/20 ,  G06F1/3237 ,  G06F1/10

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

公开(公告)号：US10296066B2

公开(公告)日：2019-05-21

申请号：US15415106

申请日：2017-01-25

Applicant: Samsung Electronics Co., LTD.

Inventor： Ah Chan Kim ,  Jae Gon Lee ,  Min Joung Lee

IPC: H04J3/06 ,  G06F1/3234 ,  G06F13/42 ,  G06F1/06 ,  H04J3/14 ,  H04L12/933

Abstract: A system on chip (SoC) includes a control circuit configured to determine whether a requested operating mode is one of a functional mode and a monitoring mode. The control circuit is configured to provide a request signal to at least one clock circuit to request at least one clock signal and selectively output one of the at least one clock signal in response to at least one acknowledgment signal received from the at least one clock circuit, when the requested operating mode is the functional mode. The control circuit is configured to selectively output one of the at least one clock signal without providing the request signal, when the requested operating mode is the monitoring mode.

公开(公告)号：US20170212549A1

公开(公告)日：2017-07-27

申请号：US15415041

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Hun Kim ,  Ah Chan Kim ,  Youn Sik Choi ,  Jae Gon Lee

IPC: G06F1/06

CPC classification number: G06F1/06 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D50/20

Abstract: A semiconductor device includes a first clock generating circuit including a first control circuit and a first clock gating circuit, a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method, a second clock generating circuit including a second control circuit and a second clock gating circuit, and a second channel management circuit which communicates with the second clock generating circuit according to the full handshake method. The first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock.

公开(公告)号：US11789515B2

公开(公告)日：2023-10-17

申请号：US17731953

申请日：2022-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Gon Lee ,  Ah Chan Kim ,  Jin Ook Song ,  Jae Young Lee ,  Youn Sik Choi

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/06 ,  G06F13/42 ,  H04J3/06 ,  H04J3/14 ,  H04L49/109 ,  G06F1/20 ,  G06F1/3237 ,  G06F1/10

CPC classification number: G06F1/3234 ,  G06F1/06 ,  G06F1/10 ,  G06F1/206 ,  G06F1/3237 ,  G06F1/3243 ,  G06F13/42 ,  H04J3/0658 ,  H04J3/14 ,  H04L49/109 ,  Y02D10/00

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.