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    MULTI-LEVEL SIGNAL GENERATOR AND MEMORY DEVICE INCLUDING THE SAME
    2.
    发明申请
    MULTI-LEVEL SIGNAL GENERATOR AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20220123759A1

    公开(公告)日：2022-04-21

    申请号：US17346220

    申请日：2021-06-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byungsuk Woo ,  Younguk Chang ,  Yongho Cho

    IPC: H03M1/12 ,  H03M1/66

    Abstract: A multi-level signal generator includes a receiving circuit, a setting circuit, a data bit generating circuit and a digital-to-analog converter. The receiving circuit generates a first data bit based on an input data signal having two voltage levels that are different from each other. The setting circuit generates a flag signal based on a command signal. The flag signal is changed depending on an operation mode. The data bit generating circuit generates a plurality of internal bits based on the first data bit, selects at least one of the plurality of internal bits based on the flag signal, and outputs the selected internal bit as at least one additional data bit. The digital-to-analog converter generates an output data signal that is a multi-level signal having three or more voltage levels different from each other based on the first data bit and the at least one additional data bit.

    Method of generating signal for test in memory device using multi-level signaling and memory device performing the same
    4.
    发明授权
    Method of generating signal for test in memory device using multi-level signaling and memory device performing the same 有权

    公开(公告)号：US11755234B2

    公开(公告)日：2023-09-12

    申请号：US17394488

    申请日：2021-08-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byungsuk Woo ,  Younguk Chang ,  Yongho Cho

    IPC: G06F3/06

    CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679

    Abstract: In a method of generating a signal for test in a memory device configured to output a multi-level signal, an operation mode is set to a first test mode. During the first test mode, first data bits included in a plurality of test data are arranged based on a first scheme. Each of the plurality of test data includes two or more data bits. During the first test mode, a first test result signal having two voltage levels is generated based on the first data bits according to the first scheme. The operation mode is set to a second test mode during which second data bits included in the plurality of test data are arranged based on a second scheme. During the second test mode, a second test result signal having the two voltage levels is generated based on the second data bits according to the second scheme.

    Multi-level signal generator and memory device including the same
    5.
    发明授权
    Multi-level signal generator and memory device including the same 有权

    公开(公告)号：US11569836B2

    公开(公告)日：2023-01-31

    申请号：US17346220

    申请日：2021-06-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byungsuk Woo ,  Younguk Chang ,  Yongho Cho

    IPC: H03M1/66 ,  H03M1/12

    Abstract: A multi-level signal generator includes a receiving circuit, a setting circuit, a data bit generating circuit and a digital-to-analog converter. The receiving circuit generates a first data bit based on an input data signal having two voltage levels that are different from each other. The setting circuit generates a flag signal based on a command signal. The flag signal is changed depending on an operation mode. The data bit generating circuit generates a plurality of internal bits based on the first data bit, selects at least one of the plurality of internal bits based on the flag signal, and outputs the selected internal bit as at least one additional data bit. The digital-to-analog converter generates an output data signal that is a multi-level signal having three or more voltage levels different from each other based on the first data bit and the at least one additional data bit.

    METHOD AND APPARATUS OF CONSTRUCTING INTERFERENCE COMPONENT AND ESTIMATING CHANNEL FOR MULTICARRIER SYSTEMS WITH NON-ORTHOGONAL WAVEFORM
    6.
    发明申请
    METHOD AND APPARATUS OF CONSTRUCTING INTERFERENCE COMPONENT AND ESTIMATING CHANNEL FOR MULTICARRIER SYSTEMS WITH NON-ORTHOGONAL WAVEFORM 审中-公开
    构造干扰成分的方法和装置以及非正交波形的MULARARRIER系统的估计通道

    公开(公告)号：US20170041097A1

    公开(公告)日：2017-02-09

    申请号：US15229032

    申请日：2016-08-04

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Kyeongyeon Kim ,  Yongho Cho ,  Chanhong Kim ,  Yeohun Yun ,  Jiyun Seol ,  Ka Ming Ho

    IPC: H04J11/00 ,  H04B7/04 ,  H04L5/00

    CPC classification number: H04J11/0023 ,  H04B7/0456 ,  H04L5/0048 ,  H04L25/023

    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A system and method for constructing an interference component using a detected data symbol and an estimated channel response in a non-orthogonal system and a method of estimating a channel using a structure of the non-orthogonal system and the interference component is disclosed. The system includes a receiver that receives a reference signal and data transmitted from a transmitter; detects adjacent data symbols around the reference signal; estimating an initial channel state; constructs the interference signal on the basis of the adjacent data symbols and the initial channel state; estimates the channel state on the basis of the constructed interference signal; and performing an iterative process of reconstructing the interference signal on the basis of the estimated channel state and re-estimates the channel state on the basis of the reconstructed interference signal.

    Abstract translation: 本公开涉及提供用于支持更高数据速率的第5代（5G）或5G通信系统超越第四代（4G）通信系统，例如长期演进（LTE）。 公开了一种使用检测到的数据符号和非正交系统中估计的信道响应来构造干扰分量的系统和方法，以及使用非正交系统和干扰分量的结构来估计信道的方法。 该系统包括接收从发射机发送的参考信号和数据的接收机; 检测参考信号周围的相邻数据符号; 估计初始信道状态; 基于相邻数据符号和初始信道状态构建干扰信号; 基于构成的干扰信号估计信道状态; 以及基于所估计的信道状态执行重建所述干扰信号的迭代处理，并且基于所述重构的干扰信号重新估计所述信道状态。

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