公开(公告)号：US10461143B2

公开(公告)日：2019-10-29

申请号：US16111210

申请日：2018-08-24

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Hyun Park ,  Sang Kyung Lee ,  Jong Moo Huh

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/52 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66

Abstract: A transistor substrate may include a base substrate, a data line, a conductive layer, a semiconductor layer, a gate electrode, and a pixel electrode. The data line may directly contact the base substrate. The conductive layer may directly contact the base substrate and may be spaced from the data line. The semiconductor layer may overlap the conductive layer, may be spaced from the conductive layer, and may include a source electrode and a drain electrode. The source electrode may be electrically connected to the data line. The gate electrode may overlap the semiconductor layer. The pixel electrode may be electrically connected to the drain electrode.

公开(公告)号：US10283533B2

公开(公告)日：2019-05-07

申请号：US15344084

申请日：2016-11-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sang Kyung Lee ,  Sang-Ho Moon

IPC: H01L27/12 ,  H01L27/32 ,  H01L21/44 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A transistor array panel includes a transistor disposed on a substrate. The transistor includes a gate electrode, a source electrode, a drain electrode, a semiconductor, and a top electrode. The top electrode is disposed on and overlaps the semiconductor, and is electrically connected to the source electrode.

公开(公告)号：US10084031B2

公开(公告)日：2018-09-25

申请号：US15630697

申请日：2017-06-22

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Hyun Park ,  Sang Kyung Lee ,  Jong Moo Huh

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/52 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/3276 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L51/5206 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/301 ,  H01L2251/308 ,  H01L2251/558

Abstract: A transistor substrate may include a base substrate, a data line, a conductive layer, a semiconductor layer, a gate electrode, and a pixel electrode. The data line may directly contact the base substrate. The conductive layer may directly contact the base substrate and may be spaced from the data line. The semiconductor layer may overlap the conductive layer, may be spaced from the conductive layer, and may include a source electrode and a drain electrode. The source electrode may be electrically connected to the data line. The gate electrode may overlap the semiconductor layer. The pixel electrode may be electrically connected to the drain electrode.