公开(公告)号：US20190130840A1

公开(公告)日：2019-05-02

申请号：US16052402

申请日：2018-08-01

Applicant: Samsung Display Co., Ltd.

Inventor： Yong Sung Park ,  Min Woo Byun ,  Kwang Chul Jung ,  Hyun Joon Kim ,  Sung Yoon Kim ,  Hyun Suk Yang ,  Doo Youl Lee

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2300/0426 ,  G09G2310/0232 ,  G09G2310/0281 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/04

Abstract: A display device includes: first pixels in a first pixel region and being connected to first scan lines; second pixels in a second pixel region that is located at a side of the first pixel region and has a width smaller than a width of the first pixel region and being connected to second scan lines; third pixels in a third pixel region that is spaced apart from the second pixel region and has a width smaller than the width of the first pixel region and being connected to third scan lines; a load matching unit in a peripheral region at an outside of the second pixel region and the third pixel region and configured to match loads of the second scan lines and the third scan lines to that of the first scan lines; and a protection unit in the peripheral region and being connected between the second and third pixels and the load matching unit.

公开(公告)号：US09698167B2

公开(公告)日：2017-07-04

申请号：US14534508

申请日：2014-11-06

Applicant: Samsung Display Co., Ltd.

Inventor： Doo Youl Lee ,  Hyuk Soon Kwon ,  Jang Soo Kim

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/1233 ,  H01L27/127 ,  H01L27/1288

Abstract: Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.

公开(公告)号：US09368518B2

公开(公告)日：2016-06-14

申请号：US14303794

申请日：2014-06-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Youl Lee ,  Se Myung Kwon ,  Hyuk Soon Kwon ,  Jang Soo Kim ,  Hyung Min Kim ,  Jin-Ho Oh

IPC: H01L27/12 ,  H01L29/417 ,  H01L21/02 ,  H01L21/768 ,  H01L29/786 ,  H01L21/3213

CPC classification number: H01L27/124 ,  H01L21/02164 ,  H01L21/02565 ,  H01L21/32139 ,  H01L21/76852 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate conductor disposed on a substrate and including a gate line and a gate electrode, a semiconductor layer overlapping the gate electrode and including an oxide semiconductor, a data conductor including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, a sidewall covering side surface parts of the drain electrode and the source electrode adjacent to a channel region of the semiconductor layer, and a passivation layer covering the source electrode, the drain electrode, and the sidewall.

Abstract translation: 薄膜晶体管阵列面板包括：栅极导体，其设置在基板上，包括栅极线和栅电极，与栅电极重叠并包括氧化物半导体的半导体层，数据导体，包括与栅极线相交的数据线， 连接到数据线的源电极和面对源电极的漏电极，覆盖与半导体层的沟道区相邻的漏电极和源电极的侧表面部分的侧壁以及覆盖源电极的钝化层 ，漏电极和侧壁。

公开(公告)号：US10580362B2

公开(公告)日：2020-03-03

申请号：US16052402

申请日：2018-08-01

Applicant: Samsung Display Co., Ltd.

Inventor： Yong Sung Park ,  Min Woo Byun ,  Kwang Chul Jung ,  Hyun Joon Kim ,  Sung Yoon Kim ,  Hyun Suk Yang ,  Doo Youl Lee

IPC: G09G3/3266

Abstract: A display device includes: first pixels in a first pixel region and connected to first scan lines; second pixels in a second pixel region that is located at a side of the first pixel region and has a width smaller than a width of the first pixel region, and connected to second scan lines; third pixels in a third pixel region that is spaced apart from the second pixel region and has a width smaller than the width of the first pixel region, and connected to third scan lines; a load matching unit in a peripheral region at an outside of the second pixel region and the third pixel region, and configured to match loads of the second scan lines and the third scan lines to that of the first scan lines; and a protection unit connected between the second and third pixels and the load matching unit.

公开(公告)号：US10483341B2

公开(公告)日：2019-11-19

申请号：US15974530

申请日：2018-05-08

Applicant: Samsung Display Co., Ltd.

Inventor： Kwang Chul Jung ,  Hyun Joon Kim ,  Sung Yoon Kim ,  Hyun Suk Yang ,  Doo Youl Lee

IPC: G09G5/02 ,  H01L27/32 ,  G09G3/3233 ,  G09G3/3275 ,  G09G3/3266 ,  G09G3/20

Abstract: A display device includes first pixels in a first pixel area and coupled with first scan lines, first scan stage circuits in a first peripheral area outside the first pixel area, and configured to supply a first scan signal to the first scan lines, second pixels in a second pixel area having a width that is less than a width of the first pixel area, and coupled with second scan lines, second scan stage circuits in a second peripheral area outside the second pixel area, and configured to generate a second scan signal, and first load matching units respectively between the second scan stage circuits, and configured to delay the second scan signal, and to supply the delayed second scan signal to the second scan lines.

公开(公告)号：US20160020230A1

公开(公告)日：2016-01-21

申请号：US14534508

申请日：2014-11-06

Applicant: Samsung Display Co., Ltd.

Inventor： Doo Youl Lee ,  Hyuk Soon Kwon ,  Jang Soo Kim

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1233 ,  H01L27/127 ,  H01L27/1288

Abstract: Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.

Abstract translation: 公开了一种薄膜晶体管阵列面板，其包括：包括显示区域和周边区域的基板; 设置在所述基板上的第二半导体层，并且设置在布置在所述显示区域和所述周边区域中的第一半导体层上; 以及设置在所述第一半导体层和所述第二半导体层上的钝化层，其中所述第一半导体层和所述第二半导体层包括氧化物半导体，并且所述第一半导体层的厚度与所述第二半导体层的厚度不同。