公开(公告)号：US20190206978A1

公开(公告)日：2019-07-04

申请号：US16298924

申请日：2019-03-11

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Keon Woo KIM ,  Ji Hyun KA ,  Tae Hoon KWON ,  Ho Kyoon KWON ,  Min Ku LEE ,  Zail LHEE ,  Jin Tae JEONG ,  Seung Ji CHA ,  Byung Du AHN ,  Jeong Ho LEE

IPC: H01L27/32 ,  H01L51/00 ,  G09G3/3233

CPC classification number: H01L27/3276 ,  G09G3/3233 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2310/0262 ,  H01L27/124 ,  H01L27/3223 ,  H01L27/3258 ,  H01L27/326 ,  H01L27/3262 ,  H01L27/3265 ,  H01L51/0096

Abstract: A display device includes a substrate including a first pixel region, a second pixel region having an area smaller than that of the first pixel region, and a peripheral region surrounding the first pixel region and the second pixel region, a second pixel provided in the second pixel region, a second line connected to the second pixel, an extension line extended to the peripheral region, a dummy part located in the peripheral region to overlap with the extension line, a power line connected to the first and second pixel regions, and a connection line located in the peripheral region to be connected to the dummy part, the connection line being electrically connected to a portion of the second pixel region, wherein the second pixel region includes a first sub-pixel region connected to the connection line and a second sub-pixel region except the first sub-pixel region.

公开(公告)号：US20150171226A1

公开(公告)日：2015-06-18

申请号：US14635732

申请日：2015-03-02

Applicant: Samsung Display Co., Ltd. ,  Kookmin University Industry Academy Cooperation Foundation

Inventor： Byung Du AHN ,  Ji Hun LIM ,  Jun Hyung LIM ,  Dae Hwan KIM ,  Jae Hyeong KIM ,  Je Hun LEE ,  Hyun Kwang JUNG

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78606 ,  H01L21/28 ,  H01L27/124 ,  H01L29/786 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.

Abstract translation: 薄膜晶体管显示面板a包括透明基板; 位于所述基板上的栅电极; 位于所述栅电极上的栅极绝缘层; 位于所述栅绝缘层上并包括沟道区的半导体层; 位于半导体层上且彼此面对的源电极和漏电极; 以及钝化层，被配置为覆盖所述源电极，所述漏电极和所述半导体层，其中所述半导体层包括在所述源电极和所述栅电极之间的相对较厚的第一部分，以及在所述漏电极和所述半导体层之间的相对较薄的第二部分 栅电极重叠，相对较厚的第一部分足够厚，以便如果第一部分与第二部分一样薄，则基本上可以减少否则可能在栅极电极到栅介质界面处发生的电荷捕获现象。

公开(公告)号：US20140291665A1

公开(公告)日：2014-10-02

申请号：US14180171

申请日：2014-02-13

Applicant: Samsung Display Co., Ltd.

Inventor： Gun Hee KIM ,  Jin Hyun PARK ,  Kyoung Won LEE ,  Byung Du AHN ,  Jee-Hun LIM ,  Jun Hyung LIM

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1288

Abstract: A thin film transistor array panel includes: a gate electrode disposed on a substrate, an insulating layer disposed on the gate electrode, an oxide semiconductor disposed on the gate insulating layer, source electrode overlapping a portion of the oxide semiconductor, a drain electrode overlapping another portion of the oxide semiconductor; and a buffer layer disposed between the oxide semiconductor and the source electrode and between the oxide semiconductor and the drain electrode. The buffer layer comprises tin as a doping material. A weight percent of the doping material is greater than approximately 0% and less than or equal to approximately 20%.

Abstract translation: 薄膜晶体管阵列面板包括：设置在基板上的栅极电极，设置在栅电极上的绝缘层，设置在栅极绝缘层上的氧化物半导体，与氧化物半导体的一部分重叠的源电极，与另一个重叠的漏电极 部分氧化物半导体; 以及设置在氧化物半导体和源电极之间以及氧化物半导体和漏电极之间的缓冲层。 缓冲层包含锡作为掺杂材料。 掺杂材料的重量百分比大于约0％且小于或等于约20％。

公开(公告)号：US20140084293A1

公开(公告)日：2014-03-27

申请号：US13798811

申请日：2013-03-13

Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION ,  SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du AHN ,  Jung Hwa KIM ,  Ji Hun LIM ,  Je Hun LEE ,  Dae Hwan KIM ,  Hyun Kwang JUNG

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78693 ,  H01L33/387

Abstract: A thin film transistor array panel includes a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a source electrode and a drain electrode on the semiconductor layer and facing each other, a floating metal layer between the source electrode and the drain electrode, and a passivation layer covering the source electrode, the drain electrode, and the floating metal layer. The floating metal layer is electrically floating.

Abstract translation: 薄膜晶体管阵列面板包括基板，基板上的栅极电极，栅电极上的栅极绝缘层，栅极绝缘层上的半导体层，半导体层上的源电极和漏电极，并面对彼此 ，源电极和漏电极之间的浮动金属层，以及覆盖源电极，漏电极和浮置金属层的钝化层。 浮动金属层电浮动。

公开(公告)号：US20130306965A1

公开(公告)日：2013-11-21

申请号：US13664180

申请日：2012-10-30

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du AHN ,  Jun Hyung LIM ,  Jin Seong PARK

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78693

Abstract: A thin film transistor includes: a gate electrode on a substrate; a source electrode; a drain electrode positioned in a same layer as the source electrode and facing the source electrode; an oxide semiconductor layer positioned between the gate electrode and the source electrode or drain electrode; and a gate insulating layer positioned between the gate electrode and the source electrode or drain electrode. The oxide semiconductor layer includes titanium oxide (TiOx) doped with niobium (Nb).

Abstract translation: 薄膜晶体管包括：衬底上的栅电极; 源电极; 位于与源电极相同的层并且面对源电极的漏电极; 位于所述栅电极和所述源电极或漏电极之间的氧化物半导体层; 以及位于栅电极和源电极或漏电极之间的栅极绝缘层。 氧化物半导体层包括掺杂有铌（Nb）的氧化钛（TiOx）。

公开(公告)号：US20220085140A1

公开(公告)日：2022-03-17

申请号：US17537237

申请日：2021-11-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Keon Woo KIM ,  Ji Hyun KA ,  Tae Hoon KWON ,  Ho Kyoon KWON ,  Min Ku LEE ,  Zail LHEE ,  Jin Tae JEONG ,  Seung Ji CHA ,  Byung Du AHN ,  Jeong Ho LEE

IPC: H01L27/32 ,  H01L51/00 ,  G09G3/3233

Abstract: A display device includes a substrate including a first pixel region, a second pixel region having an area smaller than that of the first pixel region, and a peripheral region surrounding the first pixel region and the second pixel region, a second pixel provided in the second pixel region, a second line connected to the second pixel, an extension line extended to the peripheral region, a dummy part located in the peripheral region to overlap with the extension line, a power line connected to the first and second pixel regions, and a connection line located in the peripheral region to be connected to the dummy part, the connection line being electrically connected to a portion of the second pixel region, wherein the second pixel region includes a first sub-pixel region connected to the connection line and a second sub-pixel region except the first sub-pixel region.

公开(公告)号：US20160181281A1

公开(公告)日：2016-06-23

申请号：US14813556

申请日：2015-07-30

Applicant: Samsung Display Co., Ltd.

Inventor： Dae Young LEE ,  Byung Du AHN ,  Jung Gun NAM ,  Gug Rae JO

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1262 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/7869

Abstract: A display panel comprises a substrate, a gate line, a data line insulated from the gate line, a thin film transistor electrically connected to the gate line and the data line, wherein the thin film transistor comprises a gate electrode group formed on the substrate, a gate insulating film formed on the gate electrode group, an active layer formed on the gate insulating film to at least partially overlap the gate electrode group and a source electrode and a drain electrode formed on the active layer so as to be spaced apart from each other, wherein the gate electrode group includes a first gate electrode formed on the substrate, a second gate electrode formed on the first gate electrode, and an insulating layer between the first gate electrode and the second gate electrode, and wherein the first gate electrode has reflectivity higher than that of the second gate electrode.

Abstract translation: 显示面板包括基板，栅极线，与栅极线绝缘的数据线，电连接到栅极线和数据线的薄膜晶体管，其中薄膜晶体管包括形成在基板上的栅极电极组， 形成在所述栅电极组上的栅极绝缘膜，形成在所述栅极绝缘膜上的有源层，以至少部分地与所述栅电极组重叠，以及形成在所述有源层上的源电极和漏电极，以与每个 其特征在于，所述栅电极组包括在所述基板上形成的第一栅电极，形成在所述第一栅电极上的第二栅电极，以及所述第一栅电极与所述第二栅电极之间的绝缘层， 反射率高于第二栅电极的反射率。

公开(公告)号：US20140027759A1

公开(公告)日：2014-01-30

申请号：US13733820

申请日：2013-01-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du AHN ,  Kyoung Won LEE ,  Gun Hee KIM ,  Young Joo CHOI

IPC: H01L33/44

CPC classification number: H01L33/44 ,  H01L27/1225 ,  H01L29/7869

Abstract: A display device according to an exemplary embodiment of the present invention includes a semiconductor layer; a data line disposed on the semiconductor layer, and a source electrode as well as a drain electrode disposed on the semiconductor layer and facing the source electrode. The semiconductor layer is made of an oxide semiconductor including indium, tin, and zinc. An atomic percent of indium in the oxide semiconductor is equal to or larger than about 10 at % and equal to or smaller than about 90 at %, an atomic percent of zinc in the oxide semiconductor is equal to or larger than about 5 at % and equal to or smaller than about 60 at %, and an atomic percent of tin in the oxide semiconductor is equal to or larger than about 5 at % and equal to or smaller than about 45 at %, and the data line and the drain electrode comprise copper.

Abstract translation: 根据本发明的示例性实施例的显示装置包括半导体层; 设置在半导体层上的数据线，以及设置在半导体层上并面向源电极的源电极以及漏电极。 半导体层由包括铟，锡和锌的氧化物半导体制成。 氧化物半导体中的铟的原子百分比等于或大于约10原子％且等于或小于约90原子％，氧化物半导体中的锌的原子百分比等于或大于约5原子％，以及 等于或小于约60at％，并且氧化物半导体中的锡的原子百分比等于或大于约5at％且等于或小于约45at％，并且数据线和漏电极包括 铜。

公开(公告)号：US20170053800A1

公开(公告)日：2017-02-23

申请号：US15290715

申请日：2016-10-11

Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel, Ltd.) ,  Samsung Display Co. , Ltd.

Inventor： Hiroaki TAO ,  Aya MIKI ,  Shinya MORITA ,  Satoshi YASUNO ,  Toshihiro KUGIMIYA ,  Jae Woo PARK ,  Je Hun LEE ,  Byung Du AHN ,  Gun Hee KIM

IPC: H01L21/02 ,  H01L21/477

CPC classification number: H01L21/02554 ,  G02F1/1368 ,  H01L21/02565 ,  H01L21/02587 ,  H01L21/02631 ,  H01L21/477 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7869

Abstract: The oxide of the present invention for thin-film transistors is an In—Zn—Sn-based oxide containing In, Zn, and Sn, wherein when the respective contents (atomic %) of metal elements contained in the In—Zn—Sn-based oxide are expressed by [Zn], [Sn], and [In], the In—Zn—Sn-based oxide fulfills the following expressions (2) and (4) when [In]/([In]+[Sn])≦0.5; or the following expressions (1), (3), and (4) when [In]/([In]+[Sn])>0.5. [In]/([In]+[Zn]+[Sn])≦0.3 - - - (1), [In]/([In]+[Zn]+[Sn])≦1.4×{[Zn]/([Zn]+[Sn])}−0.5 - - - (2), [Zn]/([In]+[Zn]+[Sn])≦0.83 - - - (3), and 0.1≦[In]/([In]+[Zn]+[Sn]) - - - (4). According to the present invention, oxide thin films for thin-film transistors can be obtained, which provide TFTs with excellent switching characteristics, and which have high sputtering rate in the sputtering and properly controlled etching rate in the wet etching.

Abstract translation: 用于薄膜晶体管的本发明的氧化物是含有In，Zn和Sn的In-Zn-Sn系氧化物，其中，当In-Zn-Sn系中含有的金属元素的含量（原子％ 当[In] /（[In] + [Sn]）[Zn]，[In] + [Sn]表示[Zn]，[Sn]和[In]时，In-Zn-Sn系氧化物满足下述（2） ]）≤0.5; 当[In] /（[In] + [Sn]）> 0.5时，或以下表达式（1），（3）和（4）。 [In] /（[In] + [Zn] + [Sn]）≤0.3 - - - （1），[In] /（[In] + [Zn] + [Sn]）≤1.4×{[Zn] /([Zn]+[Sn])}-0.5 - - - （2），[Zn] /（[In] + [Zn] + [Sn]）≤0.83 - - - （3）和0.1≤[ In] /（[In] + [Zn] + [Sn]） - - - （4）。 根据本发明，可以获得用于薄膜晶体管的氧化物薄膜，其提供具有优异的开关特性的TFT，并且在溅射中具有高溅射速率并且在湿蚀刻中具有适当控制的蚀刻速率。

公开(公告)号：US20140103332A1

公开(公告)日：2014-04-17

申请号：US13789335

申请日：2013-03-07

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du AHN ,  Ji Hun LIM ,  Jun Hyung LIM ,  Dae Hwan KIM ,  Jae Hyeong KIM ,  Je Hun LEE ,  Hyun Kwang JUNG

IPC: H01L29/786

CPC classification number: H01L29/78606 ,  H01L21/28 ,  H01L27/124 ,  H01L29/786 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.

Abstract translation: 薄膜晶体管显示面板a包括透明基板; 位于所述基板上的栅电极; 位于所述栅电极上的栅极绝缘层; 位于所述栅绝缘层上并包括沟道区的半导体层; 位于半导体层上且彼此面对的源电极和漏电极; 以及钝化层，被配置为覆盖所述源电极，所述漏电极和所述半导体层，其中所述半导体层包括在所述源电极和所述栅电极之间的相对较厚的第一部分，以及在所述漏电极和所述半导体层之间的相对较薄的第二部分 栅电极重叠，相对较厚的第一部分足够厚，以便如果第一部分与第二部分一样薄，则基本上可以减少否则可能在栅极电极到栅介质界面处发生的电荷捕获现象。