Abstract:
A display device includes a pixel; and a first color conversion region, a second color conversion region, and a third color conversion region respectively overlapping a first color pixel, a second color pixel, and a third color pixel and spaced from each other. The third color conversion region is aligned with a region between the first color conversion region and the second color conversion region in a first direction, and the first color conversion region and the second color conversion region are aligned with each other in a second direction crossing the first direction. Part of the first color conversion region is disposed in a second pixel area that is adjacent to the first pixel area in the second direction, and part of the second color conversion region is positioned in a third pixel area that is adjacent to the first pixel area in the second direction.
Abstract:
A display device is provided. An embodiment of a display device includes a first substrate, a second substrate disposed on the first substrate, first and second partition walls disposed on the second substrate, the second partition wall being disposed outside the first partition wall, a first trench disposed inside the first partition wall and having a first width, a second trench disposed between the first and second partition walls and having a second width greater than the first width; an alignment key disposed to overlap the second trench; a first spacer disposed on the alignment key, and a sealing member disposed along an edge between the first substrate and the second substrate without overlapping the alignment key, wherein the first spacer partially overlaps the first partition wall, the second partition wall, and the sealing member.
Abstract:
A mother substrate for a display device includes: a first mother substrate and a second mother substrate including a plurality of panel regions and facing each other; a first contact electrode and a second contact electrode on the first mother substrate; a common electrode, a first voltage application electrode and a second voltage application electrode separated from each other and on the second mother substrate; and a liquid crystal layer between the first mother substrate and the second mother substrate. The first voltage application electrode is connected to the first contact electrode, and the second voltage application electrode is connected to the second contact electrode. The first voltage application electrode is applied with a first voltage, and the second voltage application electrode is applied with a second voltage different from the first voltage.
Abstract:
A liquid crystal display includes: first and second thin film transistors and a compensation transistor formed on a first insulation substrate; a first gray subpixel electrode connected to a drain electrode of the first thin film transistor; a second gray subpixel electrode connected to a drain electrode of the compensation transistor and a drain electrode of the second thin film transistor; and first and second reference voltage lines overlapping at least one of the second gray subpixel electrode and the first gray subpixel electrode, wherein a pixel area occupied by the first gray subpixel electrode and the second gray subpixel electrode is extended in a first direction, the first and second reference voltage lines are extended in a second direction, which is substantially perpendicular to the first direction, to overlap the pixel area, and one of the first and second reference voltage lines is connected to a source electrode of the compensation transistor.
Abstract:
Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.
Abstract:
A liquid crystal display includes a first substrate, a first gate line disposed on the first substrate, a second gate line disposed on the first substrate, a data line disposed on the first substrate, a reference voltage line disposed on the first substrate and extending substantially to be parallel to the data line, a first subpixel electrode disposed in a pixel area on the first substrate, a second subpixel electrode disposed in the pixel area on the first substrate, a first switching element connected to the first gate line, the data line and the first subpixel electrode, a second switching element connected to the first gate line, the data line and the second subpixel electrode, and a third switching element connected to the first subpixel electrode and the reference voltage line.
Abstract:
A liquid crystal display includes: first and second thin film transistors and a compensation transistor formed on a first insulation substrate; a first gray subpixel electrode connected to a drain electrode of the first thin film transistor; a second gray subpixel electrode connected to a drain electrode of the compensation transistor and a drain electrode of the second thin film transistor; and first and second reference voltage lines overlapping at least one of the second gray subpixel electrode and the first gray subpixel electrode, wherein a pixel area occupied by the first gray subpixel electrode and the second gray subpixel electrode is extended in a first direction, the first and second reference voltage lines are extended in a second direction, which is substantially perpendicular to the first direction, to overlap the pixel area, and one of the first and second reference voltage lines is connected to a source electrode of the compensation transistor.
Abstract:
A thin film transistor array panel includes: a gate conductor disposed on a substrate and including a gate line and a gate electrode, a semiconductor layer overlapping the gate electrode and including an oxide semiconductor, a data conductor including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, a sidewall covering side surface parts of the drain electrode and the source electrode adjacent to a channel region of the semiconductor layer, and a passivation layer covering the source electrode, the drain electrode, and the sidewall.
Abstract:
A display device includes: a display panel including a pixel that includes a first subpixel and a second subpixel, the first subpixel displaying a first image based on a first gamma curve during a first period of a first frame and the second subpixel displaying a second image based on a second gamma curve during the first period of the first frame, where the first and second gamma curves are different; a gate driver configured to transmit a gate signal to the display panel; and a data driver configured to transmit a first data voltage based on the first gamma curve and a second data voltage based on the second gamma curve to the pixel, in which the pixel includes a voltage changing member which changes luminance of at least one of the first image and the second image during a second period of the first frame.
Abstract:
A display device is provided. An embodiment of a display device includes a first substrate, a second substrate disposed on the first substrate, first and second partition walls disposed on the second substrate, the second partition wall being disposed outside the first partition wall, a first trench disposed inside the first partition wall and having a first width, a second trench disposed between the first and second partition walls and having a second width greater than the first width; an alignment key disposed to overlap the second trench; a first spacer disposed on the alignment key, and a sealing member disposed along an edge between the first substrate and the second substrate without overlapping the alignment key, wherein the first spacer partially overlaps the first partition wall, the second partition wall, and the sealing member.