Abstract:
An LCD device includes: a first substrate; a gate line and a data line on the first substrate; at least one TFT connected to the gate and data lines and comprising source and drain electrodes; a pixel electrode connected to the TFT; a second substrate; a liquid crystal layer between the first and second substrates; a common electrode on one of the first and second substrates; a black matrix disposed on one of the first and second substrates and configured to at least partially define a pixel region; a color filter disposed to correspond to the pixel region; and a cell gap adjustment layer disposed on one of the first and second substrates and positioned so as to form different cell gaps within one pixel region.
Abstract:
A display device includes a display panel; and a light path control member disposed on the display panel, wherein the light path control member includes: a housing including a plurality of partition walls and a channel defined between two adjacent partition walls among the plurality of partition walls; a light absorbing solution configured to block transmission of light; and a first fluid transfer portion configured to control flowing of the light absorbing solution into and out of the channel.
Abstract:
A liquid crystal display device includes a lower display substrate, an upper polarizing plate and a liquid crystal layer between the lower display substrate and the upper polarizing plate. The lower display substrate includes a base substrate; a thin film transistor on the base substrate; and a color filter layer on the thin film transistor. The liquid crystal layer is disposed on the color filter layer of the lower display substrate. The upper polarizing plate is disposed on the liquid crystal layer and includes an insulating substrate, a polarizer and a protective layer which are sequentially stacked from the liquid crystal layer.
Abstract:
A liquid crystal display includes a first substrate, gate lines on the first substrate, a gate insulating layer on the gate lines, a semiconductor layer on the gate insulating layer, data lines and a drain electrode on the semiconductor layer, a passivation layer which covers the data lines and the drain electrode and in which a contact hole that partially exposes the drain electrode is defined, a common electrode above the passivation layer, a pixel electrode connected with the drain electrode through the contact hole, overlapped with the common electrode, and including a plurality of branch electrodes connected to each other through a connection portion, a contact portion extended from the connection portion and connected with the drain electrode, and a protrusion protruding toward a neighboring pixel and provided at least one corners among the connection portion or the contact portion of the pixel electrode.
Abstract:
A display device includes a substrate, a partition wall disposed on the substrate and having a plurality of openings, a first emission layer, a second emission layer, and a third emission layer respectively disposed in an opening of the partition wall and emitting light of different colors, a light blocker disposed on the emission layers and including a plurality of openings respectively overlapping the first emission layer, the second emission layer, and the third emission layer, and a color filter disposed in the opening of the light blocker. A separation distance between one edge of the partition wall contacting the second emission layer and the light blocker is greater than a separation distance between the one edge of the partition wall contacting the first emission layer and the light blocker.
Abstract:
A liquid crystal display includes: a first substrate; a gate conductor disposed on the first substrate; a gate insulating layer disposed on the gate conductor; a semiconductor layer disposed on the gate insulating layer; data line and drain electrodes disposed on the semiconductor layer, the data line including a source electrode; and a first passivation layer disposed on the data line and the drain electrode, the first passivation layer including a first contact hole. The first contact hole has a substantially circular planar shape, and wherein a first region of the drain electrode corresponding to the first contact hole has a substantially circular planar shape.
Abstract:
A liquid crystal display includes a first substrate on which a plurality of gate lines and a plurality of data lines intersecting the gate lines are disposed, a second substrate facing the first substrate, a liquid crystal layer interposed between the first and second substrates, a linear electrode on the first substrate, a surface electrode on the first substrate, an insulating layer interposed between the linear electrode and the surface electrode, a thin film transistor electrically connected to the gate and data lines and electrically connected to the linear electrode, a black matrix disposed on any one of the first and second substrates and overlapping the gate and data lines, and a voltage storage electrode extending from one end portion of the linear electrode into the black matrix and overlapping the thin film transistor.
Abstract:
A liquid crystal display includes a plurality of pixels including first, second and third pixels that display different colors and are sequentially disposed, a plurality of data lines including first, second and third data lines sequentially and repeatedly disposed where the first data line is disposed between the third pixel and the first pixel, the second data line is disposed between the first pixel and the second pixel, and the third data line is disposed between the second pixel and the third pixel, widths of the first, second and third data lines are substantially the same as each other, and a first interval between the first data line and the second data line is different from a second interval between the second data line and the third data line or a third interval between the third data line and the first data line.
Abstract:
A liquid crystal display includes: a display area including: a first data line between a first pixel electrode and a second pixel electrode in a same pixel row, and connected to a first thin film transistor (“TFT”) and a second TFT, respectively; and a peripheral area including: a first parasitic capacitor capacity measuring unit including first gate capacity units and first data capacity units; a second parasitic capacitor capacity measuring unit including second gate capacity units and second data capacity units, where a relative arrangement between the first gate and data capacity units is the same as a relative arrangement between the gate and drain electrodes of the first TFT, and a relative arrangement between the second gate and data capacity units is the same as a relative arrangement between the gate and drain electrodes of the second TFT.