公开(公告)号：US11476220B2

公开(公告)日：2022-10-18

申请号：US17146550

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin Choi ,  Jung-Hoon Han ,  Yeonjin Lee ,  Jong-Min Lee ,  Jihoon Chang

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66

Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

公开(公告)号：US12302556B2

公开(公告)日：2025-05-13

申请号：US17747423

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan Kim ,  Keonhee Park ,  Dong-Sik Park ,  Joonsuk Park ,  Jihoon Chang ,  Hyeon-Woo Jang

IPC: H01L27/108 ,  H01L21/3213 ,  H10B12/00

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including a peripheral block and cell blocks each including a cell center region, a cell edge region, and a cell middle region, and bit lines extending on each cell block in a first direction. The bit lines include center bit lines, middle bit lines, and edge bit lines. The bit line has first and second lateral surfaces opposite to each other in a second direction. The first lateral surface straightly extends along the first direction on the cell center region, the cell middle region, and the cell edge region. The second lateral surface straightly extends along the first direction on the cell center region and the cell edge region, and the second lateral surface extends along a third direction, that intersects the first direction and the second direction, on the cell middle region.

公开(公告)号：US20210305190A1

公开(公告)日：2021-09-30

申请号：US17146550

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin Choi ,  Jung-Hoon Han ,  Yeonjin Lee ,  Jong-Min Lee ,  Jihoon Chang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66

Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

公开(公告)号：US11948882B2

公开(公告)日：2024-04-02

申请号：US17964244

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Jimin Choi ,  Yeonjin Lee ,  Hyeon-Woo Jang ,  Jung-Hoon Han

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53266

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US11670559B2

公开(公告)日：2023-06-06

申请号：US17206295

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Choi ,  Jung-Hoon Han ,  Jiho Kim ,  Young-Yong Byun ,  Yeonjin Lee ,  Jihoon Chang

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L23/58 ,  H01L23/29 ,  H01L21/78

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L21/78 ,  H01L23/291 ,  H01L23/296 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/0219 ,  H01L2224/0221 ,  H01L2224/02181 ,  H01L2224/05541 ,  H01L2224/05553

Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

公开(公告)号：US11495533B2

公开(公告)日：2022-11-08

申请号：US17153963

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Jimin Choi ,  Yeonjin Lee ,  Hyeon-Woo Jang ,  Jung-Hoon Han

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US20240397705A1

公开(公告)日：2024-11-28

申请号：US18391993

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooho Shin ,  Jihoon Chang

IPC: H10B12/00

Abstract: A semiconductor device includes a device isolation pattern defining active portions extending in a first direction, a first bit line intersecting the active portions in a second direction, a second bit line spaced apart from the first bit line in a third direction, bit line capping patterns on the bit lines, a storage node contact between the bit lines, a diffusion barrier layer on sidewalls of bit lines and on a top of the storage node contact, and a landing pad on the diffusion barrier layer. A first upper end of the diffusion barrier layer on the sidewall of the first bit line is lower than the bit line capping patterns, and a second upper end of the diffusion barrier layer on the sidewall of the second bit line is lower than the first upper end.

公开(公告)号：US12072374B2

公开(公告)日：2024-08-27

申请号：US17540745

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Yeonjin Lee ,  Minjung Choi ,  Jimin Choi

IPC: G01R31/28 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: G01R31/2884 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05097 ,  H01L2224/06515

Abstract: A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.

公开(公告)号：US20230045674A1

公开(公告)日：2023-02-09

申请号：US17662306

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Woo Jang ,  Dong-Wan Kim ,  Keonhee Park ,  Dong-Sik Park ,  Joonsuk Park ,  Jihoon Chang

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.

公开(公告)号：US20250016974A1

公开(公告)日：2025-01-09

申请号：US18407789

申请日：2024-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Changsik Kim ,  Jaejoon Song

IPC: H10B12/00 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a first transistor and a second transistor on the substrate, a bit line electrically connected to the first transistor, a channel layer on the bit line, a gate insulating layer on the channel layer, a word line on the gate insulating layer, a landing pad electrically connected to the channel layer, a connection pad electrically connected to the word line and the second transistor, and a division structure separating the landing pad from the connection pad. The division structure includes an intervening portion between the landing pad and the connection pad.