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    Wafer level package for a MEMS sensor device and corresponding manufacturing process
    1.
    发明授权
    Wafer level package for a MEMS sensor device and corresponding manufacturing process 有权

    公开(公告)号：US10435290B2

    公开(公告)日：2019-10-08

    申请号：US15725190

    申请日：2017-10-04

    Applicant: STMICROELECTRONICS (MALTA) LTD

    Inventor： Conrad Cachia ,  David Oscar Vella ,  Damian Agius ,  Maria Spiteri

    IPC: B81B7/00 ,  B81C1/00 ,  H01L23/00 ,  H01L23/31

    Abstract: A MEMS device having a wafer-level package, is provided with: a stack of a first die and a second die, defining at least a first internal surface internal to the package and carrying at least an electrical contact pad, and at least a first external surface external to the package and defining a first outer face of the package; and a mold compound, at least in part coating the stack of the first and second dies and having a front surface defining at least part of a second outer face of the package, opposite to the first outer face. The MEMS device is further provided with: at least a vertical connection structure extending from the contact pad at the first internal surface towards the front surface of the mold compound; and at least an external connection element, electrically coupled to the vertical connection structure and exposed to the outside of the package, at the second outer face thereof.

    Packages for semiconductor devices and methods for assembling same
    3.
    发明授权
    Packages for semiconductor devices and methods for assembling same 有权
    半导体器件封装及组装方法

    公开(公告)号：US09527727B2

    公开(公告)日：2016-12-27

    申请号：US14498824

    申请日：2014-09-26

    Applicant: STMicroelectronics (Malta) Ltd

    Inventor： Conrad Cachia

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

    Abstract: One or more embodiments of the present disclosure are directed to packages that include a stacked microelectromechanical sensor MEMS die and an application-specific integrated circuit (ASIC) die. The smaller of the MEMS die and the ASIC die is stacked on the larger of the MEMS die and the ASIC die. The larger of the two dice may form one or more dimensions of the package. In one embodiment, a bottom surface of the larger of the two dice forms an outer surface of the package. In that regard, the package may take less lateral space on another component, such as a board or other package.

    Abstract translation: 本公开的一个或多个实施例涉及包括堆叠的微机电传感器MEMS管芯和专用集成电路（ASIC）管芯的封装。 MEMS裸片和ASIC芯片中的较小的芯片堆叠在较大的MEMS芯片和ASIC芯片上。 两个骰子中较大的一个可以形成包装的一个或多个尺寸。 在一个实施例中，两个骰子中较大者的底表面形成包装的外表面。 在这方面，包装可能在另一个部件（例如电路板或其他包装）上占用更少的横向空间。

    PACKAGES FOR SEMICONDUCTOR DEVICES AND METHODS FOR ASSEMBLING SAME
    5.
    发明申请
    PACKAGES FOR SEMICONDUCTOR DEVICES AND METHODS FOR ASSEMBLING SAME 有权
    半导体器件的封装及组装方法

    公开(公告)号：US20160090301A1

    公开(公告)日：2016-03-31

    申请号：US14498824

    申请日：2014-09-26

    Applicant: STMicroelectronics (Malta) Ltd

    Inventor： Conrad Cachia

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

    Abstract: One or more embodiments of the present disclosure are directed to packages that include a stacked microelectromechanical sensor MEMS die and an application-specific integrated circuit (ASIC) die. The smaller of the MEMS die and the ASIC die is stacked on the larger of the MEMS die and the ASIC die. The larger of the two dice may form one or more dimensions of the package. In one embodiment, a bottom surface of the larger of the two dice forms an outer surface of the package. In that regard, the package may take less lateral space on another component, such as a board or other package.

    Abstract translation: 本公开的一个或多个实施例涉及包括堆叠的微机电传感器MEMS管芯和专用集成电路（ASIC）管芯的封装。 MEMS裸片和ASIC芯片中的较小的芯片堆叠在较大的MEMS芯片和ASIC芯片上。 两个骰子中较大的一个可以形成包装的一个或多个尺寸。 在一个实施例中，两个骰子中较大者的底表面形成包装的外表面。 在这方面，包装可能在另一个部件（例如电路板或其他包装）上占用更少的横向空间。

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