Power line layout structure for semiconductor device

    公开(公告)号:US09870992B1

    公开(公告)日:2018-01-16

    申请号:US15483608

    申请日:2017-04-10

    申请人: SK hynix Inc.

    发明人: Jae Hwan Kim

    IPC分类号: H01L23/528 H01L27/108

    摘要: A power line layout structure of the semiconductor device may include first through fifth power lines. The first and second power lines may be located at a first layer, and may provide different types of power-supply voltages. The third power line may be located at a second layer disposed at a level different from that of the first layer. The third power line may be coupled to the first power line through a first contact, and may extend in the same direction as the first power line. The fourth power line may be located at the second layer, and may be coupled to the second power line through a second contact. The fourth power line may extend in the same direction as the second power line. The fifth power line may be disposed between the first power line and the second power line in the first layer.

    Power line structure for semiconductor apparatus
    2.
    发明授权
    Power line structure for semiconductor apparatus 有权
    半导体装置的电源线结构

    公开(公告)号:US09318435B2

    公开(公告)日:2016-04-19

    申请号:US14243564

    申请日:2014-04-02

    申请人: SK hynix Inc.

    摘要: A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other.

    摘要翻译: 半导体装置具有一个或多个半导体芯片。 半导体装置可以包括电源垫; 电源线设置在所述电源板的一侧,并且包括第一电力线和第二电力线; 以及连接电源板和电源线的连接线。 连接线可以包括连接电源焊盘和第一电源线的多个第一连接线和连接电源焊盘和第二电力线的多个第二连接线,并且设置在第一连接线之间。 一对或多对相邻的第一连接线可以具有连接部,通过该连接部,一对相邻的第一连接线彼此连接。

    Power line layout structure of semiconductor device and method for forming the same

    公开(公告)号:US09793210B2

    公开(公告)日:2017-10-17

    申请号:US15188052

    申请日:2016-06-21

    申请人: SK hynix Inc.

    发明人: Jae Hwan Kim

    摘要: A power line layout structure of a semiconductor device and a method for forming the same are disclosed. The power line layout structure of the semiconductor device includes a first block region including a plurality of first and second power lines, a second block region including a plurality of first and second power lines spaced apart from the first block region by a predetermined distance. Further, a first connection pattern arranged in a boundary region between the first and second block region, and formed to interconnect the first power line of the first block region and the first power line of the second block region. Still further, a second connection pattern arranged in a boundary region between the first and second block regions, and formed to interconnect the first and second block region power lines, wherein the first and second connection patterns are formed over different layers.