公开(公告)号：US20250125293A1

公开(公告)日：2025-04-17

申请号：US18789098

申请日：2024-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/367 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a substrate including: a substrate comprising a through-hole; a first semiconductor chip in the through-hole; an adhesive layer on a side surface of the first semiconductor chip in the through-hole; a first redistribution structure on an upper surface of the substrate and bonded and connected to the substrate; a second redistribution structure on a lower surface of the substrate and bonded and connected to the substrate; a second semiconductor chip on the first redistribution structure; and a through-via spaced apart from the first semiconductor chip in a horizontal direction and passing through the substrate in a vertical direction.

公开(公告)号：US20250079403A1

公开(公告)日：2025-03-06

申请号：US18666556

申请日：2024-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, the first semiconductor substrate including an active surface and an inactive surface opposite to each other, a plurality of second semiconductor chips stacked on the first semiconductor chip, each of the plurality of second semiconductor chips including a second semiconductor substrate including an active surface and an inactive surface opposite to each other, a plurality of conductive patterns on the active surface of each second semiconductor substrate of the plurality of second semiconductor chips, and a plurality of bonding pads on the inactive surface of the first semiconductor substrate and on the inactive surface of each second semiconductor substrate of the plurality of second semiconductor chips, where the plurality of bonding pads are respectively connected to the plurality of conductive patterns.

公开(公告)号：US20250125302A1

公开(公告)日：2025-04-17

申请号：US18808869

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

Abstract: A semiconductor package includes a first semiconductor chip including a plurality of upper pads, a non-conductive support layer on a top surface of the first semiconductor chip and including a plurality of openings, a second semiconductor chip on the first semiconductor chip and including a plurality of lower pads, a plurality of chip connecting terminals extending between the plurality of upper pads and the plurality of lower pads, and an insulation adhesive layer between the first semiconductor chip and the second semiconductor chip and at least partially covering the plurality of chip connecting terminals and the non-conductive support layer. A top surface of the non-conductive support layer is disposed closer to a bottom surface of the second semiconductor chip than top surfaces of the plurality of upper pads are disposed to the bottom surface of the second semiconductor chip.

公开(公告)号：US20240429198A1

公开(公告)日：2024-12-26

申请号：US18753612

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H10B80/00

Abstract: A method of manufacturing a semiconductor package according to embodiments of the present disclosure has an effect of reducing the size of the semiconductor package by minimizing a distance between semiconductor chips by self-aligning the semiconductor chips on pads having fine gaps due to the surface tension of solder bumps.

公开(公告)号：US20240421016A1

公开(公告)日：2024-12-19

申请号：US18667269

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Jing Cheng LIN ,  Jihwan SUH ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18

Abstract: A semiconductor package includes a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip, a first molding layer, a dummy chip and a second molding layer. Each second semiconductor chip includes a semiconductor substrate comprising an active surface and an inactive surface opposite to the active surface. The first molding layer surrounds a portion of an upper surface of the first semiconductor chip and side surfaces of the second semiconductor chips and includes a trench that extends from an upper surface of the first molding layer into the first molding layer. The dummy chip is stacked on an uppermost second semiconductor chip of the second semiconductor chips. The second molding layer surrounds side surfaces of the dummy chip, and covers the first molding layer.

公开(公告)号：US20250096066A1

公开(公告)日：2025-03-20

申请号：US18882385

申请日：2024-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373 ,  H01L25/18 ,  H05K1/18 ,  H10B80/00

Abstract: Provided is a semiconductor package, including a first redistribution structure, a first chip on the first redistribution structure, a molding member on the first redistribution structure and surrounding the first chip, a conductive pillar penetrating through the molding member in a first direction, a second redistribution structure on a second surface of the molding member, a second chip on the second redistribution structure, and a heat dissipation chip at least partially overlapping the first chip in the vertical direction, wherein the second redistribution structure at least partially overlaps the heat dissipation chip in a second direction intersecting the first direction.

公开(公告)号：US20250087624A1

公开(公告)日：2025-03-13

申请号：US18611241

申请日：2024-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Sungjin Han ,  Gyeongjae JO ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/00

Abstract: A semiconductor package manufacturing apparatus is provided and includes a bonding head including at least one vacuum hole, and at least one adsorption trench in a lower surface of the bonding head and connected to the at least one vacuum hole. A lower part of the bonding head includes at least one first portion, and a second portion spaced apart from the at least one first portion and surrounding the at least one first portion in a plan view. The at least one adsorption trench is defined by and between the at least one first portion and the second portion, and at least a portion of an inner surface of the at least one adsorption trench and at least a portion of an outer surface of the at least one adsorption trench are curved in the plan view.

公开(公告)号：US20250015042A1

公开(公告)日：2025-01-09

申请号：US18751869

申请日：2024-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A method of manufacturing a semiconductor package is provided. The method includes: forming a plurality of sacrificial pads on a carrier substrate and a plurality of sacrificial solder bumps on the plurality of sacrificial pads, respectively; forming a plurality of conductive pillars and a protective insulating layer on a semiconductor chip, the protective insulating layer surrounding a side surface of each of the plurality of conductive pillars; polishing the plurality of conductive pillars and the protective insulating layer to obtain a polished surface in which a surface of each of the plurality of conductive pillars is coplanar with a surface of the protective insulating layer; and bonding the plurality of conductive pillars to the plurality of sacrificial solder bumps, respectively.

公开(公告)号：US20240332256A1

公开(公告)日：2024-10-03

申请号：US18382807

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Cheng LIN ,  Young Kun JEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate including a mounting region and an edge region at least partially surrounding the mounting region, a bridge chip on a top surface of the mounting region of the package substrate, a first connection pad and a second connection pad on the mounting region of the package substrate and spaced apart from the bridge chip, a third connection pad on the edge region of the package substrate, a first mold layer on the package substrate and at least partially surrounding the bridge chip, the first connection pad, the second connection pad and the third connection pad, a first semiconductor chip on the first connection pad and the bridge chip, a second semiconductor chip on the second connection pad and the bridge chip, and a conductive post on the third connection pad.

公开(公告)号：US20250105216A1

公开(公告)日：2025-03-27

申请号：US18808787

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee ,  Jihwan Suh ,  Hyunchul Jung

IPC: H01L25/065 ,  H01L23/00

Abstract: Provided is a semiconductor package and method of manufacturing same, the semiconductor package including: a first semiconductor chip; a chip stacked structure on the first semiconductor chip, the chip stacked structure including a plurality of second semiconductor chips; a third semiconductor chip on the chip stacked structure; an adhesive layer between the chip stacked structure and the third semiconductor chip; and a first pad pattern on a lower surface of the third semiconductor chip, wherein the adhesive layer surrounds the first pad pattern and the adhesive layer is between the first pad pattern and the chip stacked structure.