公开(公告)号：US10985139B2

公开(公告)日：2021-04-20

申请号：US16151652

申请日：2018-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hun Yu ,  Tae Young Oh ,  Nam Jong Kim ,  Kwang Il Park ,  Chul Sung Park

IPC: G01K7/00 ,  G01K3/00 ,  H01L25/065 ,  H01L23/34

Abstract: In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information.

公开(公告)号：US20190171599A1

公开(公告)日：2019-06-06

申请号：US16250290

申请日：2019-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SU YEON DOO ,  Tae Young Oh

IPC: G06F13/362 ,  G06F13/40 ,  G06F13/16

Abstract: A method of operating a memory controller, memory devices including a master memory device and slave memory devices, a back channel bus coupling the master memory device to the slave memory devices and a channel coupling the memory controller to the memory devices is provided as follows. A memory command is received by the memory devices from the memory controller. An internal command is generated and outputted by the master memory device. The internal command is received by the slave memory devices. The internal command is transmitted to the slave memory devices through the back channel bus.

公开(公告)号：US10223311B2

公开(公告)日：2019-03-05

申请号：US14976865

申请日：2015-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Tae Young Oh

IPC: G06F13/36 ,  G06F13/16 ,  G06F13/40 ,  G06F13/362

Abstract: A method of operating a memory controller, memory devices including a master memory device and slave memory devices, a back channel bus coupling the master memory device to the slave memory devices and a channel coupling the memory controller to the memory devices is provided as follows. A memory command is received by the memory devices from the memory controller. An internal command is generated and outputted by the master memory device. The internal command is received by the slave memory devices. The internal command is transmitted to the slave memory devices through the back channel bus.

公开(公告)号：US09384092B2

公开(公告)日：2016-07-05

申请号：US14300289

申请日：2014-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Hyun Kim ,  Seung Jun Bae ,  Young Soo Sohn ,  Tae Young Oh ,  Won Jin Lee

IPC: G11C29/42 ,  G06F11/10 ,  G11C7/08 ,  G11C7/06 ,  G11C29/54 ,  G11C11/4091 ,  G11C11/419

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/419

Abstract: A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

Abstract translation: 半导体存储器件包括： 存储单元阵列，包括存储具有第一特性的第一数据的第一子存储单元阵列和存储具有与第一特性不同的第二特性的第二数据的第二子存储单元阵列;第一外围电路， 子存储器单元阵列，以执行指向第一子存储单元阵列的目标存储单元的读取操作和写入操作中的至少一个，以及仅与第二子存储单元阵列可操作地相关联的第二外围电路， 执行指向第二子存储单元阵列的目标存储单元的读取操作和写入操作中的至少一个。

公开(公告)号：US09607678B2

公开(公告)日：2017-03-28

申请号：US14959003

申请日：2015-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Young Oh ,  Su Yeon Doo ,  Seung Hoon Oh ,  Jong Ho Lee ,  Kwang Il Park

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40618

Abstract: A method of operating a semiconductor memory device is provided as follows. The semiconductor memory device receive a bank address for a first bank including a first word line, a second word line and a third word line. The semiconductor memory device receive a first row address to activate the first world line for a read operation or a write operation. The semiconductor memory device generates a second row address to refresh a plurality of memory cells associated with the second word line.

公开(公告)号：US09396771B2

公开(公告)日：2016-07-19

申请号：US13888409

申请日：2013-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Young Oh ,  Ho Sung Song

IPC: G11C8/12 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1048 ,  G11C8/10 ,  G11C8/12 ,  G11C2207/107

Abstract: A memory device has a burst length “b”, performs “k” core accesses per command, and receives a command, where “b” is an integer of at least 2 and “k” is an integer of at least 2 and at most “b”. The memory device includes a memory cell array including a plurality of bank groups, a plurality of bank group control units respectively corresponding to the plurality of bank groups, each of the bank group control units configured to generate a multiplexer control signal for selecting part of data read from a corresponding bank group, and a multiplexer configured to sequentially output data read from the plurality of bank groups according to the multiplexer control signal output from the plurality of bank group control units. Data items included in output data of the multiplexer have a same time space.

Abstract translation: 存储器件具有突发长度“b”，对每个命令执行“k”个核心访问，并且接收命令，其中“b”是至少为2的整数，并且“k”是至少为2的整数，并且最多 “b”。 所述存储装置包括存储单元阵列，所述存储单元阵列包括多个组组，多个组组控制单元，分别对应于所述多个组组，所述组组控制单元中的每一个被配置为生成用于选择数据的一部分的多路复用器控制信号 从对应的存储体组中读取，以及多路复用器，其被配置为根据从多个存储体组控制单元输出的多路复用器控制信号顺序地输出从多个存储体组读取的数据。 包含在多路复用器的输出数据中的数据项具有相同的时间空间。

公开(公告)号：US10719467B2

公开(公告)日：2020-07-21

申请号：US16250290

申请日：2019-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Tae Young Oh

IPC: G06F13/36 ,  G06F13/16 ,  G06F13/40 ,  G06F13/362 ,  G06F13/42

Abstract: A method of operating a memory controller, memory devices including a master memory device and slave memory devices, a back channel bus coupling the master memory device to the slave memory devices and a channel coupling the memory controller to the memory devices is provided as follows. A memory command is received by the memory devices from the memory controller. An internal command is generated and outputted by the master memory device. The internal command is received by the slave memory devices. The internal command is transmitted to the slave memory devices through the back channel bus.

公开(公告)号：US09134919B2

公开(公告)日：2015-09-15

申请号：US13837519

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Young Oh

IPC: G06F13/00 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0689 ,  G06F13/1626 ,  G06F13/1642 ,  Y02D10/14

Abstract: A memory device and a method of operating the same are provided. The memory device includes a control logic and a memory cell array. The control logic is configured to receive input information including a plurality of commands, a plurality of addresses, and priority information, and to change an execution sequence of the received commands of the input information according to the priority information. The memory cell array is configured to include a plurality of memory cells, and the memory device is configured to perform an operation on one or more memory cells based on the changed execution sequence.

Abstract translation: 提供了一种存储器件及其操作方法。 存储器件包括控制逻辑和存储单元阵列。 控制逻辑被配置为接收包括多个命令，多个地址和优先级信息的输入信息，并且根据优先级信息改变所接收的输入信息的命令的执行顺序。 存储单元阵列被配置为包括多个存储器单元，并且存储器件被配置为基于改变的执行顺序对一个或多个存储器单元执行操作。

公开(公告)号：US20130262761A1

公开(公告)日：2013-10-03

申请号：US13837519

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Young Oh

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0689 ,  G06F13/1626 ,  G06F13/1642 ,  Y02D10/14

Abstract: A memory device and a method of operating the same are provided. The memory device includes a control logic and a memory cell array. The control logic is configured to receive input information including a plurality of commands, a plurality of addresses, and priority information, and to change an execution sequence of the received commands of the input information according to the priority information. The memory cell array is configured to include a plurality of memory cells, and the memory device is configured to perform an operation on one or more memory cells based on the changed execution sequence.

Abstract translation: 提供了一种存储器件及其操作方法。 存储器件包括控制逻辑和存储单元阵列。 控制逻辑被配置为接收包括多个命令，多个地址和优先级信息的输入信息，并且根据优先级信息改变所接收的输入信息的命令的执行顺序。 存储单元阵列被配置为包括多个存储器单元，并且存储器件被配置为基于改变的执行顺序对一个或多个存储器单元执行操作。

公开(公告)号：US10529393B2

公开(公告)日：2020-01-07

申请号：US15649060

申请日：2017-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjun Shin ,  Tae Young Oh

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C29/00 ,  G11C29/02 ,  G11C7/20 ,  G11C7/04

Abstract: An exemplary embodiment includes a method of controlling a semiconductor device. The semiconductor device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, a row decoder for receiving a row address and selecting a word line corresponding to the row address, a column decoder for receiving a column address and selecting a bit line corresponding to the column address, a sense amplifier for reading data stored in a memory cell connected to the selected word line and the selected bit line, and a data output driver. The method includes setting a calibration code for a driver control code, to control an initial current strength of the data output driver, and changing the calibration code to change the driver control code during a read or write operation for the memory cell array.