公开(公告)号：US11450376B2

公开(公告)日：2022-09-20

申请号：US17038488

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

IPC: G11C11/408 ,  G11C5/06 ,  G11C11/406 ,  G11C11/4074

Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

公开(公告)号：US20180308559A1

公开(公告)日：2018-10-25

申请号：US15842029

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-Ho Kim ,  Jihwan Yu ,  Seunghyun Cho

IPC: G11C19/28 ,  G11C11/412 ,  G11C8/14 ,  H01L27/11578

CPC classification number: G11C19/28 ,  G11C5/025 ,  G11C8/14 ,  G11C11/412 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

公开(公告)号：US12198749B2

公开(公告)日：2025-01-14

申请号：US17819289

申请日：2022-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

IPC: G11C11/408 ,  G11C5/06 ,  G11C11/406 ,  G11C11/4074

Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

公开(公告)号：US20240098990A1

公开(公告)日：2024-03-21

申请号：US18127404

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd

Inventor： Sung-Min Hwang ,  Jaehoon Lee ,  Seunghyun Cho ,  Jae-Joo Shim ,  Dong-Sik Lee

IPC: H01L29/76 ,  H01L23/528

CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35

Abstract: A semiconductor device includes a gate stack structure including insulating patterns and conductive patterns which are alternately stacked, a first separation structure penetrating the gate stack structure, a second separation structure penetrating the gate stack structure and being adjacent to the first separation structure, first and second memory channel structures penetrating the gate stack structure and disposed between the first separation structure and the second separation structure, a first bit line overlapping with the first and second memory channel structures and electrically connected to the first memory channel structure, and a second bit line overlapping with the first and second memory channel structures and the first bit line and electrically connected to the second memory channel structure.

公开(公告)号：US11599458B2

公开(公告)日：2023-03-07

申请号：US17551707

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsik Sohn ,  Hyunjoong Kim ,  Woongjae Song ,  Soowoong Ahn ,  Seunghyun Cho ,  Jihyun Choi

IPC: G11C8/00 ,  G06F12/06 ,  H01L23/48 ,  H01L25/065

Abstract: According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.

公开(公告)号：US11817082B2

公开(公告)日：2023-11-14

申请号：US17276342

申请日：2019-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyu Shim ,  Seunghyun Cho ,  Sungmin Hong

IPC: G10L15/02 ,  G10L15/08 ,  G10L15/22 ,  H04R1/10 ,  H04R3/00

CPC classification number: G10L15/02 ,  G10L15/083 ,  G10L15/22 ,  H04R1/1041 ,  H04R3/005 ,  G10L2015/223 ,  G10L2015/228

Abstract: Various embodiments of the present invention relate to an electronic device for performing voice recognition using microphones selected on the basis of the operation state, and an operation method of same. According to an embodiment, the electronic device includes: one or more microphone arrays which include a plurality of microphones; at least one processor operatively connected to the microphone arrays; and at least one memory electrically connected to the processor, wherein the memory may store instructions for the processor to, at the time of execution; receive wake-up utterances, for calling designated voice services, by using a first group of microphones among the plurality of microphones when operating in a first state; operate in a second state in response to the wake-up utterances; and receive subsequent utterances using a second group of microphones among the plurality of microphones when operating in the second state. Various other embodiments are also possible.

公开(公告)号：US20220383932A1

公开(公告)日：2022-12-01

申请号：US17819289

申请日：2022-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

IPC: G11C11/408 ,  G11C5/06 ,  G11C11/406 ,  G11C11/4074

Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

公开(公告)号：US11232029B2

公开(公告)日：2022-01-25

申请号：US17003346

申请日：2020-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsik Sohn ,  Hyunjoong Kim ,  Woongjae Song ,  Soowoong Ahn ,  Seunghyun Cho ,  Jihyun Choi

IPC: G11C8/00 ,  G06F12/06 ,  H01L23/48 ,  H01L25/065

Abstract: According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.

公开(公告)号：US20250038064A1

公开(公告)日：2025-01-30

申请号：US18444477

申请日：2024-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minwoo Cho ,  Seunghyun Cho

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/498

Abstract: The present disclosure relates to chip-on-film packages. An example chip-on-film package comprises a base film including a first surface and a second surface opposite to the first surface. The base film includes a protection layer adjacent to the first surface, a film substrate adjacent to the second surface, a plurality of lead lines between the film substrate and the protection layer, and a bonding layer between the plurality of lead lines and the protection layer. The chip-on-film package includes a semiconductor chip adjacent to the first surface, and a mold layer that covers a top surface and a lateral surface of the semiconductor chip. The first surface includes a circuit surface on which the semiconductor chip is disposed and a thermal conductive surface that faces the circuit surface when the base film is bent. The thermal conductive surface is in direct contact with a top surface of the mold layer.

公开(公告)号：US20250022998A1

公开(公告)日：2025-01-16

申请号：US18583947

申请日：2024-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun Cho ,  Jaemin Jung ,  Jeongkyu Ha

IPC: H01L33/62 ,  H01L25/075 ,  H01L25/16 ,  H01L33/48

Abstract: A film package includes a film substrate, vias penetrating through the film substrate, interconnection patterns on the film substrate, and a semiconductor chip electrically connected to at least one of the interconnection patterns and to the vias, wherein the interconnection patterns include input patterns, first output patterns, and second output patterns, the film package includes input pads on a surface of the film substrate, and the input patterns extend from the input pads, the film package includes first output pads positioned toward a first edge of the film substrate on a first surface of the film substrate, and the first output patterns extend from the first output pads, and the film package includes second output pads positioned toward a second edge of the film substrate on a second surface of the film substrate opposite to the first surface, and the second output patterns extend from the second output pads.