公开(公告)号：US20250038064A1

公开(公告)日：2025-01-30

申请号：US18444477

申请日：2024-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minwoo Cho ,  Seunghyun Cho

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/498

Abstract: The present disclosure relates to chip-on-film packages. An example chip-on-film package comprises a base film including a first surface and a second surface opposite to the first surface. The base film includes a protection layer adjacent to the first surface, a film substrate adjacent to the second surface, a plurality of lead lines between the film substrate and the protection layer, and a bonding layer between the plurality of lead lines and the protection layer. The chip-on-film package includes a semiconductor chip adjacent to the first surface, and a mold layer that covers a top surface and a lateral surface of the semiconductor chip. The first surface includes a circuit surface on which the semiconductor chip is disposed and a thermal conductive surface that faces the circuit surface when the base film is bent. The thermal conductive surface is in direct contact with a top surface of the mold layer.

公开(公告)号：US20240429146A1

公开(公告)日：2024-12-26

申请号：US18639148

申请日：2024-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo Cho ,  Hyunggil Baek ,  Shlege Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a lower substrate that includes a chip mounting region and a peripheral region, where the lower substrate includes lower redistribution wirings; a first semiconductor chip on the chip mounting region, where the first semiconductor chip includes: a silicon substrate that includes a first surface and a second surface that are opposite to each other, an activation layer on the second surface, and a chip redistribution wiring layer that is on the first surface and includes a plurality of chip redistribution wirings that are electrically insulated from the activation layer; a plurality of connecting members that are on the peripheral region and are electrically connected to the lower redistribution wirings; and an upper substrate on the plurality of connecting members, and where at least a portion of the first semiconductor chip is in a through cavity defined by the upper substrate.