Abstract:
A method and memory device with in-memory computing defection detection is disclosed. A memory device includes a memory including banks, wherein each bank includes a respective plurality of bit-cells, an in-memory computation (IMC) operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device, wherein the banks share the operator, and wherein the memory device is configured to: generate a first test pattern that is stored in the memory and generate a second test pattern applied to the IMC operator, and based thereon determine whether a defect has occurred in either the memory or the operator, and perform a repair based on the determination that a defect has occurred.
Abstract:
A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.
Abstract:
A converter and a circuit device including the converter are disclosed. The converter includes an inductor including a first end and a second end, and a switching circuit connected to the inductor. The switching circuit includes a first switch to control a connection between the first end and a battery connected to the converter, a second switch to control a connection between the second end and a current output end configured to output a current generated through the inductor from the battery, a third switch to control a connection between the second end and a voltage output end configured to output a voltage generated from the battery, and a fourth switch to control a connection between the second end and a voltage input end configured to receive a voltage to charge the battery.
Abstract:
Provided are a voltage generating method and apparatus. A wireless power device includes a boosting circuit configured to generate a high voltage, and a switch arrangement circuit configured to selectively transmit energy to the boosting circuit, for the generating of the high voltage, using an inductor included in a resonator and in response to a build-up request for the high voltage.
Abstract:
A single-inductor multiple-output (SIMO) converter includes a converter configured to provide respective voltages of a plurality of channels with a single inductor and a control logic configured to control switches of the converter based on clocks corresponding to the plurality of channels, wherein the control logic is configured to compare an output voltage of a selected channel of the plurality of channels that corresponds to a control target to a reference voltage of the selected channel based on a clock of the selected channel and operate in one of a first mode that adaptively adjusts a number of times that a pulse triggering a power transfer to the channel is generated, and a second mode that blocks a generation of the pulse.
Abstract:
A method of performing a predetermined operation for a circuit that includes a resistor group, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, and a parasitic capacitance existing at each node between resistors of the resistor group. The method includes in a forward process, determining a time when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage as a switching time; at the switching time, connecting the sampling capacitor to a ground or predetermined voltage and floating the power supply unit; in a backward process, after the switching time, determining a time when a power supply unit voltage applied to the power supply unit reaches a second reference voltage as an end time; and performing the predetermined operation based on the end time.
Abstract:
A boost converter and a cell applicable to the boost converter are provided. The cell comprises a control circuit configured to generate a bottom control signal related to a bottom plate of a capacitor, and a top control signal related to a top plate of the capacitor to connect the capacitor based on one or more operational phases, and a booster configured to convert the top control signal generated by the control circuit, wherein the capacitor is configured to be sequentially connected to voltage levels through switches, based on the bottom control signal and the converted top control signal.
Abstract:
A wireless power transmission system includes: a wireless power transmission apparatus including: a transmission coil configured to form mutual coupling with an auxiliary coil disposed outside of a living body; and a controller configured to control a supply of power by a power source to the transmission coil to wirelessly transmit the power from the transmission coil, using the auxiliary coil, to a wireless power reception apparatus disposed inside the living body through the mutual coupling, wherein a distance between the transmission coil and the auxiliary coil is adjustable.
Abstract:
A method of evaluating a physiological aging level includes calculating a complexity corresponding to a change pattern of a physiological parameter sensed from a user, and determining an aging level indicating a physiological change progress of the user based on the complexity.
Abstract:
A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.