Memory and method with in-memory computing defect detection

    公开(公告)号:US12198775B2

    公开(公告)日:2025-01-14

    申请号:US18091258

    申请日:2022-12-29

    Abstract: A method and memory device with in-memory computing defection detection is disclosed. A memory device includes a memory including banks, wherein each bank includes a respective plurality of bit-cells, an in-memory computation (IMC) operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device, wherein the banks share the operator, and wherein the memory device is configured to: generate a first test pattern that is stored in the memory and generate a second test pattern applied to the IMC operator, and based thereon determine whether a defect has occurred in either the memory or the operator, and perform a repair based on the determination that a defect has occurred.

    Converter device and method
    3.
    发明授权

    公开(公告)号:US11848564B2

    公开(公告)日:2023-12-19

    申请号:US16657245

    申请日:2019-10-18

    CPC classification number: H02J50/10 H02J50/12 H02M3/04 A61B5/0538 A61B5/686

    Abstract: A converter and a circuit device including the converter are disclosed. The converter includes an inductor including a first end and a second end, and a switching circuit connected to the inductor. The switching circuit includes a first switch to control a connection between the first end and a battery connected to the converter, a second switch to control a connection between the second end and a current output end configured to output a current generated through the inductor from the battery, a third switch to control a connection between the second end and a voltage output end configured to output a voltage generated from the battery, and a fourth switch to control a connection between the second end and a voltage input end configured to receive a voltage to charge the battery.

    Voltage generating method and apparatus

    公开(公告)号:US10581265B2

    公开(公告)日:2020-03-03

    申请号:US15440384

    申请日:2017-02-23

    Abstract: Provided are a voltage generating method and apparatus. A wireless power device includes a boosting circuit configured to generate a high voltage, and a switch arrangement circuit configured to selectively transmit energy to the boosting circuit, for the generating of the high voltage, using an inductor included in a resonator and in response to a build-up request for the high voltage.

    METHOD AND APPARATUS PERFORMING OPERATIONS USING CIRCUITS

    公开(公告)号:US20210405967A1

    公开(公告)日:2021-12-30

    申请号:US17093889

    申请日:2020-11-10

    Abstract: A method of performing a predetermined operation for a circuit that includes a resistor group, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, and a parasitic capacitance existing at each node between resistors of the resistor group. The method includes in a forward process, determining a time when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage as a switching time; at the switching time, connecting the sampling capacitor to a ground or predetermined voltage and floating the power supply unit; in a backward process, after the switching time, determining a time when a power supply unit voltage applied to the power supply unit reaches a second reference voltage as an end time; and performing the predetermined operation based on the end time.

    Processing device and electronic device having the same

    公开(公告)号:US12141687B2

    公开(公告)日:2024-11-12

    申请号:US17195917

    申请日:2021-03-09

    Abstract: A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.

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