公开(公告)号：US20170018479A1

公开(公告)日：2017-01-19

申请号：US15168242

申请日：2016-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul SAGONG ,  Sang-Woo PAE ,  Seung-Jin CHOO

IPC: H01L23/367 ,  H01L29/423 ,  H01L29/06 ,  H01L27/092 ,  H01L23/373

CPC classification number: H01L23/367 ,  B82Y10/00 ,  H01L23/3731 ,  H01L23/3738 ,  H01L27/0211 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a thermal conduction layer on the substrate, a first wire pattern on the thermal conduction layer, a first semiconductor pattern a second semiconductor pattern, and a gate electrode between the first semiconductor pattern and the second semiconductor pattern. The gate electrode surrounds a periphery of the first wire pattern. A concentration of impurity of the thermal conduction layer is different from that of the substrate. The first wire pattern includes a first end and a second end. The concentration of impurity contained in the first wire pattern is higher than that contained in the thermal conduction layer and that contained in the substrate. The first semiconductor pattern is in contact with the first end of the first wire pattern and the thermal conduction layer. The second semiconductor pattern is in contact with the second end of the first wire pattern.

Abstract translation: 半导体器件包括衬底，衬底上的导热层，导热层上的第一布线图案，第一半导体图案，第二半导体图案以及第一半导体图案和第二半导体图案之间的栅电极。 栅电极围绕第一线图案的周边。 导热层的杂质浓度与基板的杂质浓度不同。 第一线图案包括第一端和第二端。 包含在第一线图案中的杂质的浓度高于在导热层中包含的和包含在基底中的杂质的浓度。 第一半导体图案与第一布线图案的第一端和导热层接触。 第二半导体图案与第一线图案的第二端接触。

公开(公告)号：US20180091122A1

公开(公告)日：2018-03-29

申请号：US15584448

申请日：2017-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Won SHIM ,  Dong-Uk PARK ,  Phil-Jae JEON ,  Sang-Woo PAE ,  Da AHN

IPC: H03K3/66 ,  H03K19/00 ,  H03K5/19

CPC classification number: H03K3/66 ,  G06F1/04 ,  H03K5/135 ,  H03K5/19 ,  H03K19/0002

Abstract: A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.

公开(公告)号：US20160365326A1

公开(公告)日：2016-12-15

申请号：US15145231

申请日：2016-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Sang CHO ,  Sang-Woo PAE ,  Hyun-Suk CHUN ,  Young-Seok JUNG

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L27/092

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/585 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02235 ,  H01L2224/0235 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/0231 ,  H01L2224/11

Abstract: A semiconductor device comprises a semiconductor chip which includes at least one gate structure on a substrate, the gate structure including a first region, a second region different from the first region, and a third region between the first and the second region, a first redistribution layer on a top surface of the semiconductor chip, the first redistribution layer configured to electrically connect a first electrode pad of the semiconductor chip to a first solder ball and overlap the first region of the gate structure, a second redistribution layer on the top surface of the semiconductor chip, the second redistribution layer configured to electrically connect a second electrode pad of the semiconductor chip to a second solder ball and overlap the second region of the gate structure such that the third region is exposed, and an insulating layer on the first redistribution layer and the second redistribution layer.

Abstract translation: 半导体器件包括半导体芯片，其包括在衬底上的至少一个栅极结构，所述栅极结构包括第一区域，与第一区域不同的第二区域以及第一和第二区域之间的第三区域，第一再分布 所述第一再分配层被配置为将所述半导体芯片的第一电极焊盘电连接到第一焊球并与所述栅极结构的所述第一区域重叠，所述第二再分配层在所述第一焊盘的顶表面上 所述半导体芯片，所述第二再分配层被配置为将所述半导体芯片的第二电极焊盘电连接到第二焊球，并且与所述栅极结构的所述第二区域重叠以使得所述第三区域被暴露，以及在所述第一重新分布上的绝缘层 层和第二再分布层。