公开(公告)号：US20220059514A1

公开(公告)日：2022-02-24

申请号：US17198763

申请日：2021-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-WON LEE

IPC: H01L25/10 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a first sub-semiconductor package, an interposer substrate, and a second sub-semiconductor package that are sequentially stacked. The first sub-semiconductor package includes a first package substrate, a first semiconductor device, and a first mold member that are sequentially stacked, and the interposer substrate includes at least one hole. The first mold member includes: a mold main portion which covers the first semiconductor device; a mold connecting portion extended from the mold main portion and inserted into the at least one hole; and a mold protruding portion extended from the mold connecting portion to cover a top surface of the interposer substrate outside the at least one hole. The mold main portion, the mold connecting portion, and the mold protruding portion constitute a single object.

公开(公告)号：US20230187285A1

公开(公告)日：2023-06-15

申请号：US17883250

申请日：2022-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANG-WON LEE ,  HYUNKI KIM ,  YOUNG-JA KIM ,  HYUNGGIL BAEK

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/12 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/75621 ,  H01L2224/75001 ,  H01L2224/81194 ,  H01L2224/8118

Abstract: A method of manufacturing a semiconductor package includes estimating an error in a solder ball attaching process, determining a specification of a ball tool and a method of the solder ball attaching process, based on the estimated error, manufacturing the ball tool according to the determined specification thereof, and performing the solder ball attaching process based on the method of the solder ball attaching process. The determining of the specification of the ball tool and the method of the solder ball attaching process includes determining a number of a plurality of holders in the ball tool and a position and a width of each of the plurality of holders, determining a number of a plurality of working regions of a substrate and a position and a width of each of the plurality of working regions, and dividing a substrate into the plurality of working regions.

公开(公告)号：US20250029864A1

公开(公告)日：2025-01-23

申请号：US18439884

申请日：2024-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KANG GYUNE LEE ,  SANG-WON LEE ,  HYEON HWANG ,  Younhwan SHIN

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/687

Abstract: A chuck table includes a support part receiving a package substrate. The package substrate includes a package area having semiconductor packages arranged thereon and a scrap area surrounding the package area. A package pad part is between the support part and the package substrate and directly contacts the package area. A scrap pad part is disposed between the support part and the package substrate and directly contacts the scrap area. A vacuum pipe extends through the package pad part and extends into the support part. The vacuum pipe has vacuum pressure applied thereto and has the vacuum pressure released therefrom. A fixing device is connected to the vacuum pipe. The fixing device moves closer to an upper surface of the scrap area as the vacuum pressure is applied to the vacuum pipe, and moves away from the upper surface of the scrap area as the vacuum pressure is released.

公开(公告)号：US20230120252A1

公开(公告)日：2023-04-20

申请号：US17735158

申请日：2022-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAE HWAN KIM ,  HYUNG GIL BAEK ,  YOUNG-JA KIM ,  KANG GYUNE LEE ,  SANG-WON LEE ,  YONG KWAN LEE

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.