公开(公告)号：US09627492B2

公开(公告)日：2017-04-18

申请号：US14964758

申请日：2015-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhwan Kim ,  Jaehyun Jung ,  Jungkyung Kim ,  Kyuok Lee ,  Jaejune Jang ,  Changki Jeon ,  Suyeon Cho ,  Seonghoon Ko ,  Kyu-Heon Cho

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/402 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/7816

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, an epitaxial layer having a second conductivity type, an isolation area in the epitaxial layer to define an active area of the semiconductor substrate, a body area having a first conductivity type and a drift area having a second conductivity type adjacent to each other in the epitaxial layer, a LOCOS insulating layer in the drift area and surrounded by the drift area, a drain area adjacent to a side part of the LOCOS insulating layer and surrounded by the drift area, a body contact area and a source area in the body area and surrounded by the body area, and a gate area overlapping the drift area and a part of the LOCOS insulating layer from a direction of the body area.

公开(公告)号：US12002890B2

公开(公告)日：2024-06-04

申请号：US17585284

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyun Yoo ,  Kyuok Lee ,  Uihui Kwon ,  Junhyeok Kim ,  Yongwoo Jeon ,  Dawon Jeong ,  Jaehyok Ko

IPC: H01L29/86 ,  H01L29/06 ,  H01L29/40 ,  H01L29/861

CPC classification number: H01L29/861 ,  H01L29/0634 ,  H01L29/404 ,  H01L29/0649

Abstract: A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.