Abstract:
A semiconductor memory device includes an external resistor provided on a board and a plurality of memory dies mounted on the board, designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation during an initialization sequence of the semiconductor memory device and stores, in a first register set therein, first calibration data, a first voltage and a first temperature. Each of the slave dies, after the first impedance calibration operation is completed, performs a second impedance calibration operation during the initialization sequence and stores, in a second register set therein, second calibration data associated with the second impedance calibration operation and offset data corresponding to a difference between the first calibration data and the second calibration data.
Abstract:
A memory system according to example embodiments of the inventive concept may include a storage device and a memory device. The storage device includes a first interface circuit configured to be connected to a processor and a second interface circuit different from the first interface circuit. The memory device includes a third interface circuit configured to be connected to the processor based on a DRAM interface, a fourth interface circuit configured to be different from the third interface circuit and configured to be connected to the second interface circuit, and a random access memory divided into a first memory area and a second memory area. The first memory area is accessed by the processor through the third interface circuit and the second memory area is accessed by the storage device through the second interface circuit and the fourth interface circuit.
Abstract:
A semiconductor memory device includes; a memory semiconductor die including a volatile memory device configured to perform a normal operation in response to at least one of a command and an address received from a host device, and a test chip vertically stacked with the memory semiconductor die and including a nonvolatile memory device. The test chip is configured in the normal mode to store log information corresponding to at least one of a command and an address received by the semiconductor memory device from the host device, and is further configured in a debugging mode to read the log information from the nonvolatile memory device.
Abstract:
An electronic device according to various embodiments may include: a housing, an acoustic hole formed in a first direction of the housing, an instrument installed in the housing in a second direction perpendicular to the first direction, a mic, and a mic holder including a body installed in the housing, a seat formed in the body part to receive the mic, a first opening formed in one surface of the body and connected to the seat, a second opening formed in another surface of the body, and a third opening formed in the body and connected to the acoustic hole. As the second opening of the mic holder is closed by an instrument of the electronic device closely attached to the other surface of the body part, an acoustic channel in which a sound introduced into the third opening is delivered to a mic hole of the mic may be formed.
Abstract:
An electronic device includes a display module. The electronic device also includes an input interface configured to be functionally connected to the electronic, to transmit an input detection signal to the electronic device by detecting an input of additional input unit formed at a side, and to transmit to the electronic device at least one of a movement signal generated by detecting a movement while an input of the additional input unit is maintained and a scroll signal generated by detecting an input of a scroll unit installed at a side. The electronic device further includes a processor configured to receive an input detection signal from the input interface, to receive at least one of the movement signal and the scroll signal while the input of the additional input unit is maintained, and to control a user interface based on the received signal.
Abstract:
An electronic device is provided The electronic device includes a first case member, a plurality of protruding members provided on the first case member or a supporting member disposed on the first case member, at least one speaker, an enclosure configured to receive at least a portion of the speaker and including a plurality of receiving recesses formed in a side surface of the enclosure, and engaging members engaged to the enclosure and at least partially positioned in the receiving recesses, respectively. The engaging members may be engaged to one of the plurality of protruding members, respectively, to fix the enclosure to the first case member or the support member disposed on the first case member. Other various embodiments are possible as well.
Abstract:
An electronic device includes a memory and a system on chip (SoC). The memory device includes a first memory cell area assigned to a first channel and a second memory cell area assigned to a second channel. The SoC includes a first processing unit and a second processing unit. The first processing unit is configured to transmit a first command for accessing the first memory cell area to the memory device through the first channel. The second processing unit is configured to transmit a second command for accessing the second memory cell area to the memory device through the second channel. The memory device is configured such that a bandwidth of the first channel and a bandwidth of the second channel are different from each other.
Abstract:
A window display method and apparatus of an electronic device is provided for displaying windows according to a signal input from an external input device. When a predetermined input of a function key is received for generating a new window within a display screen from the external input device, during a window generation mode, generating and displaying the new window including at least one of menu items, icons, and files that are preselected when such a request for generating a window is received from the external input device.
Abstract:
A memory device includes a first volatile memory chip that includes a first volatile memory cell array storing first data and that receives or outputs the first data at a first bandwidth, and a second volatile memory chip that includes a second volatile memory cell array storing second data and that receives or outputs the second data at a second bandwidth different from the first bandwidth.
Abstract:
A memory system according to example embodiments of the inventive concept may include a storage device and a memory device. The storage device includes a first interface circuit configured to be connected to a processor and a second interface circuit different from the first interface circuit. The memory device includes a third interface circuit configured to be connected to the processor based on a DRAM interface, a fourth interface circuit configured to be different from the third interface circuit and configured to be connected to the second interface circuit, and a random access memory divided into a first memory area and a second memory area. The first memory area is accessed by the processor through the third interface circuit and the second memory area is accessed by the storage device through the second interface circuit and the fourth interface circuit.