公开(公告)号：US09269420B2

公开(公告)日：2016-02-23

申请号：US14253353

申请日：2014-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kichul Chun ,  Hyun-Chul Yoon

IPC: G11C11/24 ,  G11C11/4094 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4074

CPC classification number: G11C11/4094 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4074 ,  G11C11/4091

Abstract: A semiconductor memory device is provided. A cell array includes a DRAM cell connected to one of a pair of bit lines. A bit line sense amplifier is coupled to the pair of bit lines. The bit line sense amplifier discharges a low-level bit line of the pair of bit lines toward a ground level and clamps the low-level bit line to a boosted sense ground voltage in response to a control signal. A sense amplifier control logic generates the control signal having a pulse interval. The low-level bit line is discharged toward the ground level for the pulse interval and after the pulse interval ends, the low-level bit line is clamped to the boosted sense ground voltage.

Abstract translation: 提供半导体存储器件。 单元阵列包括连接到一对位线之一的DRAM单元。 位线读出放大器耦合到一对位线。 位线读出放大器将一对位线的低电平位线朝向接地电平放电，并且响应于控制信号将低电平位线钳位到升压检测接地电压。 读出放大器控制逻辑产生具有脉冲间隔的控制信号。 低电平位线在脉冲间隔内向地电平放电，脉冲间隔结束后，低电平位线被钳位到升压检测接地电压。